forked from M-Labs/artiq-zynq
zc706: add CXP FMC variant
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@ -25,6 +25,7 @@ import analyzer
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import acpki
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import acpki
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import drtio_aux_controller
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import drtio_aux_controller
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import zynq_clocking
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import zynq_clocking
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import coaxpress_4r
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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class SMAClkinForward(Module):
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class SMAClkinForward(Module):
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@ -648,6 +649,14 @@ class _NIST_QC2_RTIO:
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self.add_rtio(rtio_channels)
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self.add_rtio(rtio_channels)
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class _CXP_FMC_RTIO():
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"""
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CoaXpress FMC with 4 CXP channel and 1 SMA trigger
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"""
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def __init__(self):
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platform = self.platform
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platform.add_extension(coaxpress_4r.fmc_adapter_io)
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class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
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class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
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def __init__(self, acpki, drtio100mhz):
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def __init__(self, acpki, drtio100mhz):
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ZC706.__init__(self, acpki)
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ZC706.__init__(self, acpki)
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@ -680,8 +689,14 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
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_SatelliteBase.__init__(self, acpki, drtio100mhz)
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_SatelliteBase.__init__(self, acpki, drtio100mhz)
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_NIST_QC2_RTIO.__init__(self)
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_NIST_QC2_RTIO.__init__(self)
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class CXP_FMC(ZC706, _CXP_FMC_RTIO):
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def __init__(self, acpki, drtio100mhz):
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ZC706.__init__(self, acpki)
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self.submodules += SMAClkinForward(self.platform)
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_CXP_FMC_RTIO.__init__(self)
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VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
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VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
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NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
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NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite, CXP_FMC]}
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def main():
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def main():
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parser = argparse.ArgumentParser(
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parser = argparse.ArgumentParser(
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