forked from M-Labs/artiq-zynq
CXP gtx: rename to CXP DownConn
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@ -10,7 +10,7 @@ from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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from coaxpress_clock_align import CXP_BruteforceClockAligner
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from coaxpress_clock_align import CXP_BruteforceClockAligner
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class CXP_GTX(Module):
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class CXP_DownConn(Module):
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# Settings:
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# Settings:
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# * GTX reference clock @ 125MHz
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# * GTX reference clock @ 125MHz
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# * GTX data width = 20
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# * GTX data width = 20
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@ -348,7 +348,7 @@ class CXP(Module, AutoCSR):
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# # #
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# # #
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# single CXP
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# single CXP
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self.submodules.gtx = gtx = CXP_GTX(refclk, pads, sys_clk_freq, tx_mode="single", rx_mode="single")
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self.submodules.gtx = gtx = CXP_DownConn(refclk, pads, sys_clk_freq, tx_mode="single", rx_mode="single")
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# ! loopback for debugging
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# ! loopback for debugging
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self.sync += gtx.loopback_mode.eq(self.loopback_mode.storage)
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self.sync += gtx.loopback_mode.eq(self.loopback_mode.storage)
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