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CXP gtx: rename to CXP DownConn

This commit is contained in:
morgan 2024-06-14 17:07:58 +08:00
parent b52589bd5f
commit d592825284
1 changed files with 2 additions and 2 deletions

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@ -10,7 +10,7 @@ from artiq.gateware.drtio.transceiver.gtx_7series_init import *
from coaxpress_clock_align import CXP_BruteforceClockAligner from coaxpress_clock_align import CXP_BruteforceClockAligner
class CXP_GTX(Module): class CXP_DownConn(Module):
# Settings: # Settings:
# * GTX reference clock @ 125MHz # * GTX reference clock @ 125MHz
# * GTX data width = 20 # * GTX data width = 20
@ -348,7 +348,7 @@ class CXP(Module, AutoCSR):
# # # # # #
# single CXP # single CXP
self.submodules.gtx = gtx = CXP_GTX(refclk, pads, sys_clk_freq, tx_mode="single", rx_mode="single") self.submodules.gtx = gtx = CXP_DownConn(refclk, pads, sys_clk_freq, tx_mode="single", rx_mode="single")
# ! loopback for debugging # ! loopback for debugging
self.sync += gtx.loopback_mode.eq(self.loopback_mode.storage) self.sync += gtx.loopback_mode.eq(self.loopback_mode.storage)