From d5928252847d1c07b2d57ebe849c3d9a3541e0e2 Mon Sep 17 00:00:00 2001 From: morgan Date: Fri, 14 Jun 2024 17:07:58 +0800 Subject: [PATCH] CXP gtx: rename to CXP DownConn --- src/gateware/coaxpress_gtx.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gateware/coaxpress_gtx.py b/src/gateware/coaxpress_gtx.py index 09388ce..8e0252a 100644 --- a/src/gateware/coaxpress_gtx.py +++ b/src/gateware/coaxpress_gtx.py @@ -10,7 +10,7 @@ from artiq.gateware.drtio.transceiver.gtx_7series_init import * from coaxpress_clock_align import CXP_BruteforceClockAligner -class CXP_GTX(Module): +class CXP_DownConn(Module): # Settings: # * GTX reference clock @ 125MHz # * GTX data width = 20 @@ -348,7 +348,7 @@ class CXP(Module, AutoCSR): # # # # single CXP - self.submodules.gtx = gtx = CXP_GTX(refclk, pads, sys_clk_freq, tx_mode="single", rx_mode="single") + self.submodules.gtx = gtx = CXP_DownConn(refclk, pads, sys_clk_freq, tx_mode="single", rx_mode="single") # ! loopback for debugging self.sync += gtx.loopback_mode.eq(self.loopback_mode.storage)