diff --git a/src/gateware/coaxpress_gtx.py b/src/gateware/coaxpress_gtx.py
index 09388ce..8e0252a 100644
--- a/src/gateware/coaxpress_gtx.py
+++ b/src/gateware/coaxpress_gtx.py
@@ -10,7 +10,7 @@ from artiq.gateware.drtio.transceiver.gtx_7series_init import *
 
 from coaxpress_clock_align import CXP_BruteforceClockAligner
 
-class CXP_GTX(Module):
+class CXP_DownConn(Module):
     # Settings:
     # * GTX reference clock @ 125MHz
     # * GTX data width = 20
@@ -348,7 +348,7 @@ class CXP(Module, AutoCSR):
         # # #
 
         # single CXP 
-        self.submodules.gtx = gtx = CXP_GTX(refclk, pads, sys_clk_freq, tx_mode="single", rx_mode="single")
+        self.submodules.gtx = gtx = CXP_DownConn(refclk, pads, sys_clk_freq, tx_mode="single", rx_mode="single")
         
         # ! loopback for debugging
         self.sync += gtx.loopback_mode.eq(self.loopback_mode.storage)