forked from M-Labs/artiq-zynq
cxp GW: pipeine update docs
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@ -122,8 +122,8 @@ class DownConn_Interface(Module, AutoCSR):
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# Receiver Pipeline WIP
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# Receiver Pipeline WIP
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#
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#
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# 32 32+8(dchar)
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# 32 32+8(dchar)
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# PHY ---/---> dchar -----/-----> trigger ack ------> packet ------> CDC FIFO ------> debug buffer
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# PHY ---/---> dchar -----/-----> trigger ack ------> packet ------> CDC FIFO ------> raw stream data packet without
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# decoder checker decoder
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# decoder checker decoder the first 2 words (K27.7 & 0x01)
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#
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#
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cdr = ClockDomainsRenamer("cxp_gtx_rx")
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cdr = ClockDomainsRenamer("cxp_gtx_rx")
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