morgan/artiq-zynq
1
0
Fork 0
forked from M-Labs/artiq-zynq
Code Pull Requests Activity

pipeline GW: rename word_dw to word_width

Browse Source
This commit is contained in:
morgan 2025-01-14 15:22:17 +08:00
parent 8589436937
commit d46b617c30
1 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/gateware/cxp_pipeline.py
View File

@ -10,12 +10,12 @@ from operator import or_, and_
char_width = 8
char_layout = [("data", char_width), ("k", char_width//8)]
word_dw = 32
word_layout = [("data", word_dw), ("k", word_dw//8)]
word_width = 32
word_layout = [("data", word_width), ("k", word_width//8)]
word_layout_dchar = [
("data", word_dw),
("k", word_dw//8),
("data", word_width),
("k", word_width//8),
("dchar", char_width),
("dchar_k", char_width//8),
]
@ -211,7 +211,7 @@ class Control_Packet_Writer(Module):
# # #
self.specials.mem = mem = Memory(word_dw, buffer_depth)
self.specials.mem = mem = Memory(word_width, buffer_depth)
self.specials.mem_port = mem_port = mem.get_port()
self.source = stream.Endpoint(word_layout)
@ -291,8 +291,8 @@ class RX_Debug_Buffer(Module,AutoCSR):
self.inc = CSR()
self.dout_valid = CSRStatus()
self.dout_pak = CSRStatus(word_dw)
self.kout_pak = CSRStatus(word_dw//8)
self.dout_pak = CSRStatus(word_width)
self.kout_pak = CSRStatus(word_width//8)
self.crc_error = CSRStatus()
self.eop = CSRStatus()
@ -493,7 +493,7 @@ class Control_Packet_Reader(Module):
]
# A circular buffer for firmware to read packet from
self.specials.mem = mem = Memory(word_dw, buffer_count*buffer_depth)
self.specials.mem = mem = Memory(word_width, buffer_count*buffer_depth)
self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
# buffered mem_port to improve timing