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downconn GW: move DRP csr inside of this module

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morgan 2025-01-24 13:10:59 +08:00
parent d663f4d263
commit d1c1777645
1 changed files with 26 additions and 0 deletions
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26
src/gateware/cxp_downconn.py
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@ -19,6 +19,14 @@ class CXP_RXPHYs(Module, AutoCSR):
self.gtx_start_init = CSRStorage()
self.gtx_restart = CSR()
# DRP port
self.gtx_daddr = CSRStorage(9)
self.gtx_dread = CSR()
self.gtx_din_stb = CSR()
self.gtx_din = CSRStorage(16)
self.gtx_dout = CSRStatus(16)
self.gtx_dready = CSR()
self.phys = []
# # #
@ -43,7 +51,25 @@ class CXP_RXPHYs(Module, AutoCSR):
for i, phy in enumerate(self.phys):
if i == master:
self.comb += rx_resetter.rx_ready.eq(phy.gtx.rx_ready)
# Connect master GTX connections' output DRP
self.sync += [
If(phy.gtx.dready,
self.gtx_dready.w.eq(1),
self.gtx_dout.status.eq(phy.gtx.dout),
).Elif(self.gtx_dready.re,
self.gtx_dready.w.eq(0),
),
]
# Connect all GTX connections' input DRP
self.sync += [
phy.gtx.daddr.eq(self.gtx_daddr.storage),
phy.gtx.den.eq(self.gtx_dread.re | self.gtx_din_stb.re),
phy.gtx.dwen.eq(self.gtx_din_stb.re),
phy.gtx.din.eq(self.gtx_din.storage),
]
self.comb += [
phy.gtx.dclk.eq(ClockSignal("sys")),
phy.gtx.rx_manual_restart.eq(self.gtx_restart.re | rx_resetter.rx_reset),
phy.gtx.rx_init.clk_path_ready.eq(self.gtx_start_init.storage),
]