diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py
index d1ad658..58afdf4 100755
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@@ -25,7 +25,7 @@ import analyzer
 import acpki
 import drtio_aux_controller
 import zynq_clocking
-import coaxpress_4r
+import coaxpress_4r, coaxpress_gtx
 from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 
 class SMAClkinForward(Module):
@@ -139,7 +139,7 @@ class ZC706(SoCCore):
         platform.add_extension(si5324_fmc33)
         self.comb += platform.request("si5324_33").rst_n.eq(1)
 
-        cdr_clk = Signal()
+        self.cdr_clk = Signal()
         cdr_clk_buf = Signal()
         si5324_out = platform.request("si5324_clkout")
         platform.add_period_constraint(si5324_out.p, 8.0)
@@ -147,11 +147,11 @@ class ZC706(SoCCore):
             Instance("IBUFDS_GTE2",
                 i_CEB=0,
                 i_I=si5324_out.p, i_IB=si5324_out.n,
-                o_O=cdr_clk,
+                o_O=self.cdr_clk,
                 p_CLKCM_CFG="TRUE",
                 p_CLKRCV_TRST="TRUE",
                 p_CLKSWING_CFG=3),
-            Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
+            Instance("BUFG", i_I=self.cdr_clk, o_O=cdr_clk_buf)
         ]
         self.config["HAS_SI5324"] = None
         self.config["SI5324_AS_SYNTHESIZER"] = None
@@ -658,6 +658,15 @@ class _CXP_FMC_RTIO():
         platform.add_extension(coaxpress_4r.fmc_adapter_io)
         platform.add_extension(leds_fmc33)
 
+        clk_freq = 125e6
+
+        self.submodules.cxp_gtx = coaxpress_gtx.CXP(
+            refclk=self.cdr_clk,
+            pads=platform.request("CXP_HS", 0),
+            sys_clk_freq=clk_freq
+        )
+        self.csr_devices.append("cxp_gtx")
+
         rtio_channels = []
         # FIXME remove this placeholder RTIO channel
         # There are too few RTIO channels and cannot be compiled (adr width issue of the lane distributor)