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cxp GW: cleanup debug csr

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morgan 2025-02-07 14:40:58 +08:00
parent a6ad4501b1
commit cdfd365f85
1 changed files with 20 additions and 50 deletions
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70
src/gateware/cxp.py
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@ -290,17 +290,11 @@ class CXP_Grabber(Module, AutoCSR):
def __init__(self, host, roi_engine_count=8, res_width=16, count_width=31):
assert count_width <= 31
self.crc_error_cnt = CSRStatus(16)
self.crc_error_reset = CSR()
self.crc_error = CSR()
self.roi_counter = CSRStatus(count_width)
self.roi_update = CSR()
self.pix_y = CSRStatus(res_width)
self.header_l_size = CSRStatus(3*char_width)
self.header_x_size = CSRStatus(3*char_width)
self.header_y_size = CSRStatus(3*char_width)
self.header_new_line = CSRStatus(3*char_width)
self.frame_pixel_format = CSRStatus(3*char_width)
self.frame_x_size = CSRStatus(3*char_width)
self.frame_y_size = CSRStatus(3*char_width)
# # #
@ -319,7 +313,7 @@ class CXP_Grabber(Module, AutoCSR):
# ROI rtio
# 4 cfg (x0, y0, x1, y1) per roi_engine
# 4 configs (x0, y0, x1, y1) per roi_engine
self.config = rtlink.Interface(rtlink.OInterface(res_width, bits_for(4*roi_engine_count-1)))
# select which roi engine can output rtio_input signal
@ -329,7 +323,6 @@ class CXP_Grabber(Module, AutoCSR):
rtlink.IInterface(count_width+1, timestamped=False)
)
# # #
cdr = ClockDomainsRenamer("cxp_gt_rx")
@ -342,23 +335,25 @@ class CXP_Grabber(Module, AutoCSR):
self.submodules.broadcaster = broadcaster = cdr(Stream_Broadcaster())
self.submodules.buffer = buffer = cdr(Buffer(word_layout_dchar)) # to improve timing
self.submodules.stream2pix = stream2pix = cdr(Stream2Pixel4x(res_width, count_width))
# CRC error counter
self.submodules.crc_reset_ps = crc_reset_ps = PulseSynchronizer("sys", "cxp_gt_rx")
self.comb += crc_reset_ps.i.eq(self.crc_error_reset.re)
crc_error_cnt_rx = Signal.like(self.crc_error_cnt.status)
crc_error_r = Signal()
self.sync.cxp_gt_rx += [
# to improve timinig
crc_error_r.eq(stream2pix.crc_checker.error),
# Frame metadata
metadata = stream2pix.header_reader.metadata
self.specials += [
MultiReg(metadata.x_size, self.frame_x_size.status),
MultiReg(metadata.y_size, self.frame_y_size.status),
MultiReg(metadata.pixel_format, self.frame_pixel_format.status),
]
If(crc_reset_ps.o,
crc_error_cnt_rx.eq(crc_error_cnt_rx.reset),
).Elif(crc_error_r,
crc_error_cnt_rx.eq(crc_error_cnt_rx + 1),
# CRC error
self.submodules.crc_error_ps = crc_error_ps = PulseSynchronizer("cxp_gt_rx", "sys")
self.sync.cxp_gt_rx += crc_error_ps.i.eq(stream2pix.crc_checker.error)
self.sync += [
If(crc_error_ps.o,
self.crc_error.w.eq(1),
).Elif(self.crc_error.re,
self.crc_error.w.eq(0),
),
]
self.specials += MultiReg(crc_error_cnt_rx, self.crc_error_cnt.status)
# Connecting the pipeline
self.comb += [
@ -386,31 +381,6 @@ class CXP_Grabber(Module, AutoCSR):
self.sync.rio += If(self.gate_data.o.stb,
serializer.gate.eq(self.gate_data.o.data))
# DEBUG:
l_size_rx, l_size_sys = Signal(3*char_width), Signal(3*char_width)
x_size_rx, x_size_sys = Signal(3*char_width), Signal(3*char_width)
y_size_rx, y_size_sys = Signal(3*char_width), Signal(3*char_width)
y_pix_rx, y_pix_sys = Signal(res_width), Signal(res_width)
self.sync.cxp_gt_rx += [
l_size_rx.eq(stream2pix.header_reader.metadata.l_size),
x_size_rx.eq(stream2pix.header_reader.metadata.x_size),
y_size_rx.eq(stream2pix.header_reader.metadata.y_size),
y_pix_rx.eq(stream2pix.pixel4x[0].y),
]
self.specials += [
MultiReg(l_size_rx, l_size_sys),
MultiReg(x_size_rx, x_size_sys),
MultiReg(y_size_rx, y_size_sys),
MultiReg(y_pix_rx, y_pix_sys),
]
self.sync += [
self.pix_y.status.eq(y_pix_sys),
self.header_l_size.status.eq(l_size_sys),
self.header_x_size.status.eq(x_size_sys),
self.header_y_size.status.eq(y_size_sys),
]
class CXP_Synchronizer(Module):
def __init__(self, roi_engines):
counts_in = [roi_engine.out.count for roi_engine in roi_engines]