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cxp upconn: add sys_clk_freq parameter to set pll

This commit is contained in:
morgan 2024-06-20 16:20:27 +08:00
parent e6550c68cf
commit cdc7294e99
1 changed files with 3 additions and 3 deletions
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6
src/gateware/cxp_upconn.py
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@ -6,7 +6,7 @@ from misoc.interconnect.csr import *
from misoc.interconnect import stream from misoc.interconnect import stream
class CXP_UpConn(Module, AutoCSR): class CXP_UpConn(Module, AutoCSR):
def __init__(self, pads, tx_fifo_depth=32): def __init__(self, pads, sys_clk_freq, tx_fifo_depth=32):
self.clock_domains.cd_cxp_upconn = ClockDomain() self.clock_domains.cd_cxp_upconn = ClockDomain()
self.clk_reset = CSRStorage(reset=1) self.clk_reset = CSRStorage(reset=1)
self.bitrate2x_enable = CSRStorage() self.bitrate2x_enable = CSRStorage()
@ -26,11 +26,11 @@ class CXP_UpConn(Module, AutoCSR):
o_LOCKED=pll_locked, o_LOCKED=pll_locked,
i_RST=ResetSignal("sys"), i_RST=ResetSignal("sys"),
p_CLKIN1_PERIOD=8, # ns p_CLKIN1_PERIOD=1e9/sys_clk_freq, # ns
i_CLKIN1=ClockSignal("sys"), i_CLKIN1=ClockSignal("sys"),
# VCO @ 1.25GHz # VCO @ 1.25GHz
p_CLKFBOUT_MULT=10, p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=1.25e9/sys_clk_freq, p_DIVCLK_DIVIDE=1,
i_CLKFBIN=pll_fb_clk, o_CLKFBOUT=pll_fb_clk, i_CLKFBIN=pll_fb_clk, o_CLKFBOUT=pll_fb_clk,
# 20.83MHz (48ns) # 20.83MHz (48ns)