From cdc7294e99804b86d53ae5acc7380f31a1632eeb Mon Sep 17 00:00:00 2001 From: morgan Date: Thu, 20 Jun 2024 16:20:27 +0800 Subject: [PATCH] cxp upconn: add sys_clk_freq parameter to set pll --- src/gateware/cxp_upconn.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gateware/cxp_upconn.py b/src/gateware/cxp_upconn.py index bff8d54..e9d46aa 100644 --- a/src/gateware/cxp_upconn.py +++ b/src/gateware/cxp_upconn.py @@ -6,7 +6,7 @@ from misoc.interconnect.csr import * from misoc.interconnect import stream class CXP_UpConn(Module, AutoCSR): - def __init__(self, pads, tx_fifo_depth=32): + def __init__(self, pads, sys_clk_freq, tx_fifo_depth=32): self.clock_domains.cd_cxp_upconn = ClockDomain() self.clk_reset = CSRStorage(reset=1) self.bitrate2x_enable = CSRStorage() @@ -26,11 +26,11 @@ class CXP_UpConn(Module, AutoCSR): o_LOCKED=pll_locked, i_RST=ResetSignal("sys"), - p_CLKIN1_PERIOD=8, # ns + p_CLKIN1_PERIOD=1e9/sys_clk_freq, # ns i_CLKIN1=ClockSignal("sys"), # VCO @ 1.25GHz - p_CLKFBOUT_MULT=10, p_DIVCLK_DIVIDE=1, + p_CLKFBOUT_MULT=1.25e9/sys_clk_freq, p_DIVCLK_DIVIDE=1, i_CLKFBIN=pll_fb_clk, o_CLKFBOUT=pll_fb_clk, # 20.83MHz (48ns)