forked from M-Labs/artiq-zynq
cxp downconn: replace QPLL with CPLL
cxp downconn: add QPLL with its reset CSR cxp downconn: set QPLL as CLK source for GTX cxp downconn: remove PLL_reset signal from tx_init to prevent race condition cxp downconn: rename cxp_gtx to GTX
This commit is contained in:
parent
563e06ca8d
commit
ccd3e6618a
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@ -24,17 +24,29 @@ class CXP_DownConn(Module, AutoCSR):
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self.rxinit_phaligndone = CSRStatus()
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self.rxinit_phaligndone = CSRStatus()
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self.rx_ready = CSRStatus()
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self.rx_ready = CSRStatus()
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self.qpll_reset = CSR()
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self.qpll_locked = CSRStatus()
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# # #
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# # #
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# TODO: QPLL (GTXE2_COMMON) here
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self.submodules.qpll = QPLL(refclk, sys_clk_freq)
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# CPLL too slow for 12.5Gbps :(
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# single & master tx_mode can lock with rx in loopback
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# single & master tx_mode can lock with rx in loopback
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self.submodules.gtx = CXP_GTX(refclk, pads, sys_clk_freq, tx_mode="single", rx_mode="single")
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self.submodules.gtx = GTX(refclk, self.qpll, pads, sys_clk_freq, tx_mode="single", rx_mode="single")
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# TEST: txusrclk alignment
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# 1) use GTREFCLK with TXSYSCLKSEL = 0b10 -> still inconsistant
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# 2) tie qpllPDEN with ~qpll.reset, -> inconsistant
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# 3) seems like tx_init gtxXreset fall too soon (cplllock hold hi too long) <--- this a cross clk domain issue :<
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self.comb += [
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self.sync += [
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# PLL
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self.qpll.reset.eq(self.qpll_reset.re),
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self.qpll_locked.status.eq(self.qpll.lock),
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# GTX
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self.txinit_phaligndone.status.eq(self.gtx.tx_init.Xxphaligndone),
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self.txinit_phaligndone.status.eq(self.gtx.tx_init.Xxphaligndone),
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# self.rxinit_phaligndone.status.eq(self.gtx.rx_init.Xxphaligndone),
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self.rxinit_phaligndone.status.eq(self.gtx.rx_init.Xxphaligndone),
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self.rx_ready.status.eq(self.gtx.rx_ready),
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self.rx_ready.status.eq(self.gtx.rx_ready),
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self.gtx.txenable.eq(self.txenable.storage[0]),
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self.gtx.txenable.eq(self.txenable.storage[0]),
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@ -52,7 +64,17 @@ class CXP_DownConn(Module, AutoCSR):
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# DEBUG:SMA
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# DEBUG:SMA
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self.specials += [
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self.specials += [
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Instance("OBUF", i_I=self.gtx.rxoutclk, o_O=debug_sma.p_tx),
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Instance("OBUF", i_I=self.gtx.rxoutclk, o_O=debug_sma.p_tx),
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Instance("OBUF", i_I=self.gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx)
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Instance("OBUF", i_I=self.gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
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# pmod 0-7 pin
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Instance("OBUF", i_I=self.qpll.lock, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=self.qpll.reset, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=self.gtx.tx_init.gtXxreset, o_O=pmod_pads[2]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[3]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[4]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[6]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[7]),
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]
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]
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# DEBUG: datain
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# DEBUG: datain
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@ -117,6 +139,88 @@ class CXP_DownConn(Module, AutoCSR):
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# checkout channel interfaces & drtio_gtx
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# checkout channel interfaces & drtio_gtx
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# checkout GTPTXPhaseAlignement for inspiration
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# checkout GTPTXPhaseAlignement for inspiration
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class QPLL(Module):
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def __init__(self, refclk, sys_clk_freq):
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self.clk = Signal()
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self.refclk = Signal()
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self.lock = Signal()
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self.reset = Signal()
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# # #
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# WARNING: VCO cannot do 12.5GHz on ZC706
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# VCO freq = sys*qpll_fbdiv
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# PLL output = VCO/2
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qpll_fbdiv = 0b0100100000
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qpll_fbdiv_ratio = 1
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fbdiv_real = 80
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refclk_div = 1
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self.Xxout_div = 4
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self.tx_usrclk_freq = (sys_clk_freq*fbdiv_real/self.Xxout_div)/20
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# QPLL reset
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pll_reset_cycles = ceil(sys_clk_freq/125e6)
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pll_reset_timer = WaitTimer(pll_reset_cycles)
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self.submodules += pll_reset_timer
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reset = Signal()
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startup_fsm = FSM(reset_state="IDLE")
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self.submodules += startup_fsm
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startup_fsm.act("IDLE",
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If(self.reset, NextState("RESET_PLL"))
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)
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startup_fsm.act("RESET_PLL",
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reset.eq(1),
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pll_reset_timer.wait.eq(1),
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If(pll_reset_timer.done, NextState("IDLE"))
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)
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self.specials += [
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Instance("GTXE2_COMMON",
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i_QPLLREFCLKSEL=0b001,
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i_GTREFCLK0=refclk,
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i_QPLLPD=0,
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i_QPLLRESET=reset,
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i_QPLLLOCKEN=1,
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o_QPLLLOCK=self.lock,
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o_QPLLOUTCLK=self.clk,
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o_QPLLOUTREFCLK=self.refclk,
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# See UG476 (v1.12.1) Table 2-16
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p_QPLL_FBDIV=qpll_fbdiv,
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p_QPLL_FBDIV_RATIO=qpll_fbdiv_ratio,
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p_QPLL_REFCLK_DIV=refclk_div,
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# From 7 Series FPGAs Transceivers Wizard
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p_BIAS_CFG=0x0000040000001000,
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p_COMMON_CFG=0x00000000,
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p_QPLL_CFG=0x0680181,
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p_QPLL_CLKOUT_CFG=0b0000,
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p_QPLL_COARSE_FREQ_OVRD=0b010000,
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p_QPLL_COARSE_FREQ_OVRD_EN=0b0,
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p_QPLL_CP=0b0000011111,
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p_QPLL_CP_MONITOR_EN=0b0,
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p_QPLL_DMONITOR_SEL=0b0,
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p_QPLL_FBDIV_MONITOR_EN= 0b0,
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p_QPLL_INIT_CFG=0x000006,
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p_QPLL_LOCK_CFG=0x21E8,
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p_QPLL_LPF=0b1111,
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# Reserved, values cannot be modified
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i_BGBYPASSB=0b1,
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i_BGMONITORENB=0b1,
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i_BGPDB=0b1,
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i_BGRCALOVRD=0b11111,
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i_RCALENB=0b1,
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i_QPLLRSVD1=0b0,
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i_QPLLRSVD2=0b11111,
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)
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]
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# Changes the phase of the transceiver RX clock to align the comma to
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# Changes the phase of the transceiver RX clock to align the comma to
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# the LSBs of RXDATA, fixing the latency.
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# the LSBs of RXDATA, fixing the latency.
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#
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#
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@ -224,26 +328,20 @@ class CXP_BruteforceClockAligner(Module):
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class CXP_GTX(Module):
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class GTX(Module):
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# Settings:
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# Settings:
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# * GTX reference clock @ 125MHz
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# * GTX reference clock @ 125MHz
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# * GTX data width = 20
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# * GTX data width = 20
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# * GTX PLL frequency @ 3.125GHz
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# * GTX PLL frequency @ 3.125GHz
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# * GTX line rate (TX & RX) @ 3.125Gb/s
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# * GTX line rate (TX & RX) @ 3.125Gb/s
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# * GTX TX/RX USRCLK @ PLL/datawidth = 156MHz
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# * GTX TX/RX USRCLK @ PLL/datawidth = 156MHz
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def __init__(self, refclk, pads, sys_clk_freq, tx_mode="single", rx_mode="single"):
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def __init__(self, refclk, qpll, pads, sys_clk_freq, tx_mode="single", rx_mode="single"):
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assert tx_mode in ["single", "master", "slave"]
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assert tx_mode in ["single", "master", "slave"]
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assert rx_mode in ["single", "master", "slave"]
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assert rx_mode in ["single", "master", "slave"]
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cpll_div = 4
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# linerate = USRCLK * datawidth
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cpll_div45 = 5
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refclk_div = 1
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Xxout_div = 2
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# linerate = sys * cpll_mult
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cpll_mult = 2 * cpll_div * cpll_div45 / (Xxout_div * refclk_div)
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pll_fbout_mult = 10
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pll_fbout_mult = 10
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txusr_pll_div = pll_fbout_mult*20/cpll_mult # 20 is datawidth
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txusr_pll_div = pll_fbout_mult*sys_clk_freq/qpll.tx_usrclk_freq # 20 is datawidth
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self.rx_restart = Signal()
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self.rx_restart = Signal()
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self.tx_restart = Signal()
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self.tx_restart = Signal()
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@ -262,16 +360,16 @@ class CXP_GTX(Module):
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# # #
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# # #
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cpllreset = Signal()
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cplllock = Signal()
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# TX generates cxp_tx clock, init must be in system domain
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# TX generates cxp_tx clock, init must be in system domain
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self.submodules.tx_init = tx_init = GTXInit(sys_clk_freq, False, mode=tx_mode)
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self.submodules.tx_init = tx_init = GTXInit(sys_clk_freq, False, mode=tx_mode)
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# RX receives restart commands from RTIO domain
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# RX receives restart commands from RTIO domain
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self.submodules.rx_init = rx_init = ClockDomainsRenamer("cxp_gtx_tx")(GTXInit(sys_clk_freq, True, mode=rx_mode))
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self.submodules.rx_init = rx_init = ClockDomainsRenamer("cxp_gtx_tx")(GTXInit(qpll.tx_usrclk_freq, True, mode=rx_mode))
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# DEBUG: change back to cxp_gtx_tx once QPLL works
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# self.submodules.rx_init = rx_init = GTXInit(sys_clk_freq, True, mode=rx_mode)
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self.comb += [
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self.comb += [
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cpllreset.eq(tx_init.cpllreset),
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tx_init.cplllock.eq(qpll.lock),
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tx_init.cplllock.eq(cplllock),
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rx_init.cplllock.eq(qpll.lock)
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rx_init.cplllock.eq(cplllock)
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]
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]
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txdata = Signal(20)
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txdata = Signal(20)
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@ -293,29 +391,21 @@ class CXP_GTX(Module):
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p_PD_TRANS_TIME_FROM_P2=0x3c,
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p_PD_TRANS_TIME_FROM_P2=0x3c,
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p_PD_TRANS_TIME_NONE_P2=0x3c,
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p_PD_TRANS_TIME_NONE_P2=0x3c,
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p_PD_TRANS_TIME_TO_P2=0x64,
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p_PD_TRANS_TIME_TO_P2=0x64,
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i_CPLLPD=1,
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# CPLL
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# QPLL
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p_CPLL_CFG=0xBC07DC,
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i_QPLLCLK=qpll.clk,
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p_CPLL_FBDIV=cpll_div,
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i_QPLLREFCLK=qpll.refclk,
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p_CPLL_FBDIV_45=cpll_div45,
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p_RXOUT_DIV=qpll.Xxout_div,
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p_CPLL_REFCLK_DIV=refclk_div,
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p_TXOUT_DIV=qpll.Xxout_div,
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p_RXOUT_DIV=Xxout_div,
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i_RXSYSCLKSEL=0b11, # use QPLL & QPLL's REFCLK
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p_TXOUT_DIV=Xxout_div,
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i_TXSYSCLKSEL=0b11, # use QPLL & CPLL's REFCLK
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p_CPLL_INIT_CFG=0x00001E,
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p_CPLL_LOCK_CFG=0x01E8,
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i_CPLLRESET=cpllreset,
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i_CPLLPD=cpllreset,
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o_CPLLLOCK=cplllock,
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i_CPLLLOCKEN=1,
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i_CPLLREFCLKSEL=0b001,
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i_TSTIN=2**20-1,
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i_GTREFCLK0=refclk,
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# TX clock
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# TX clock
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p_TXBUF_EN="FALSE",
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p_TXBUF_EN="FALSE",
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p_TX_XCLK_SEL="TXUSR",
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p_TX_XCLK_SEL="TXUSR",
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o_TXOUTCLK=self.txoutclk,
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o_TXOUTCLK=self.txoutclk,
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i_TXSYSCLKSEL=0b00,
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# i_TXSYSCLKSEL=0b00,
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i_TXOUTCLKSEL=0b11,
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i_TXOUTCLKSEL=0b11,
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# TX Startup/Reset
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# TX Startup/Reset
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@ -386,7 +476,7 @@ class CXP_GTX(Module):
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# RX clock
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# RX clock
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i_RXDDIEN=1,
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i_RXDDIEN=1,
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i_RXSYSCLKSEL=0b00,
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# i_RXSYSCLKSEL=0b00,
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i_RXOUTCLKSEL=0b010,
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i_RXOUTCLKSEL=0b010,
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o_RXOUTCLK=self.rxoutclk,
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o_RXOUTCLK=self.rxoutclk,
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i_RXUSRCLK=ClockSignal("cxp_gtx_rx"),
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i_RXUSRCLK=ClockSignal("cxp_gtx_rx"),
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@ -531,7 +621,7 @@ class CXP_GTX(Module):
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# 125MHz: align <1s
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# 125MHz: align <1s
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# 156.25MHz: align <15s
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# 156.25MHz: align <15s
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# 250MHz: cannot align
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# 250MHz: cannot align
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clock_aligner = CXP_BruteforceClockAligner(0b0101111100, 1_000_000)
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clock_aligner = CXP_BruteforceClockAligner(0b0101111100, 800_000)
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self.submodules += clock_aligner
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self.submodules += clock_aligner
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self.comb += [
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self.comb += [
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clock_aligner.rxdata.eq(rxdata),
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clock_aligner.rxdata.eq(rxdata),
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