forked from M-Labs/artiq-zynq
downconn GW: fix timing violation
testing tx: add buffer to improve timing testing tx: send idle more frequently downconn GW: remove unneeded stb signal downconn GW: add docs
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@ -56,9 +56,12 @@ class Receiver(Module):
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self.source = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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data_valid = Signal()
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self.sync.cxp_gtx_rx += [
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self.sync.cxp_gtx_rx += [
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data_valid.eq(gtx.comma_checker.rxfsm.ongoing("READY")),
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self.source.stb.eq(0),
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self.source.stb.eq(0),
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If(gtx.rx_ready & self.source.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1)),
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If(data_valid & self.source.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1)),
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self.source.stb.eq(1),
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self.source.stb.eq(1),
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self.source.data.eq(Cat(gtx.decoders[i].d for i in range(4))),
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self.source.data.eq(Cat(gtx.decoders[i].d for i in range(4))),
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self.source.k.eq(Cat(gtx.decoders[i].k for i in range(4))),
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self.source.k.eq(Cat(gtx.decoders[i].k for i in range(4))),
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@ -66,17 +69,22 @@ class Receiver(Module):
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]
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]
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# DEBUG: tx fifos for loopback
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# DEBUG: tx fifos for loopback
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# fw -> fifo (sys) -> cdc fifo -> gtx tx
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# fw -> -> cdc fifo -> buffered fifo -> gtx tx
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tx_fifo = stream.AsyncFIFO(word_layout, 512)
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cdc_fifo = stream.AsyncFIFO(word_layout, 512)
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self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(tx_fifo)
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self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(cdc_fifo)
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self.sink = tx_fifo.sink
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self.sink = cdc_fifo.sink
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self.tx_stb_sys = Signal()
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# fix timing violation
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txstb = Signal()
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cdr = ClockDomainsRenamer("cxp_gtx_tx")
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self.specials += MultiReg(self.tx_stb_sys, txstb, odomain="cxp_gtx_tx")
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self.submodules.buf = tx_fifo = cdr(stream.SyncFIFO(word_layout, 2, buffered=True))
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word_count = Signal(max=100)
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self.comb += [
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cdc_fifo.source.connect(tx_fifo.sink),
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]
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idle_period = 50 # press in word
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word_count = Signal(max=idle_period)
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# JANK: fix the every 98th word got eaten
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# JANK: fix the every 98th word got eaten
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# cnt 97 98 99 0
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# cnt 97 98 99 0
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@ -85,11 +93,11 @@ class Receiver(Module):
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self.sync.cxp_gtx_tx += [
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self.sync.cxp_gtx_tx += [
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tx_fifo.source.ack.eq(0),
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tx_fifo.source.ack.eq(0),
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If(word_count == 99,
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If(word_count == idle_period-1,
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word_count.eq(word_count.reset),
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word_count.eq(word_count.reset),
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).Else(
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).Else(
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If(tx_fifo.source.stb & txstb,
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If(tx_fifo.source.stb,
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If(word_count != 98, tx_fifo.source.ack.eq(1)),
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If(word_count != idle_period-2, tx_fifo.source.ack.eq(1)),
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word_count.eq(word_count + 1),
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word_count.eq(word_count + 1),
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)
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)
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)
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)
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@ -97,7 +105,7 @@ class Receiver(Module):
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# NOTE: prevent the first word send twice due to stream stb delay
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# NOTE: prevent the first word send twice due to stream stb delay
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self.comb += [
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self.comb += [
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If((tx_fifo.source.stb & tx_fifo.source.ack & (word_count != 99)),
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If((tx_fifo.source.stb & tx_fifo.source.ack & (word_count != idle_period-1)),
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gtx.encoder.d[0].eq(tx_fifo.source.data[:8]),
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gtx.encoder.d[0].eq(tx_fifo.source.data[:8]),
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gtx.encoder.d[1].eq(tx_fifo.source.data[8:16]),
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gtx.encoder.d[1].eq(tx_fifo.source.data[8:16]),
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gtx.encoder.d[2].eq(tx_fifo.source.data[16:24]),
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gtx.encoder.d[2].eq(tx_fifo.source.data[16:24]),
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