diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index 8442845..0c5b26b 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -203,36 +203,44 @@ class DownConn_Interface(Module, AutoCSR):
         # Priority level 2 packet - data, test packet
         self.submodules.packet_decoder = packet_decoder = cdr(CXP_Data_Packet_Decode())
 
+        self.new_rx_packet = CSR()
+        self.decoder_error = CSR()
+        self.test_error = CSR()
+
+        self.submodules.new_packet_ps = new_packet_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
         self.submodules.decode_err_ps = decode_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
         self.submodules.test_err_ps = test_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
         self.comb += [
+            new_packet_ps.i.eq(packet_decoder.new_packet),
             decode_err_ps.i.eq(packet_decoder.decode_err),
             test_err_ps.i.eq(packet_decoder.test_err),
         ]
-
-        self.packet_type = CSRStatus(8)
-        self.decoder_error = CSR()
-        self.test_error = CSR()
-        # self.read_pointer = CSR()
-
-        self.specials += MultiReg(packet_decoder.packet_type, self.packet_type.status)
         self.sync += [
+            If(new_packet_ps.o,
+                self.new_rx_packet.w.eq(1),
+            ).Elif(self.new_rx_packet.re,
+                self.new_rx_packet.w.eq(0),
+            ),
             If(decode_err_ps.o,
-               self.decoder_error.w.eq(1),
+                self.decoder_error.w.eq(1),
             ).Elif(self.decoder_error.re,
-               self.decoder_error.w.eq(0),
+                self.decoder_error.w.eq(0),
             ),
             If(test_err_ps.o,
                 self.test_error.w.eq(1),
             ).Elif(self.test_error.re,
                 self.test_error.w.eq(0),
             ),
-            # FIXME: this cannot be routed
-            # self.read_pointer.w.eq(packet_decoder.read_ptr_rx),
-            # If(self.read_pointer.re, 
-            #     packet_decoder.read_ptr_rx.eq(packet_decoder.read_ptr_rx + 1),
-            # ),
-            
+        ]
+
+
+        # Cicular buffer interface
+        self.packet_type = CSRStatus(8)
+        self.write_pointer = CSRStatus(bits_for(buffer_depth)) # for firmware to sync with buffer
+
+        self.specials += [
+            MultiReg(packet_decoder.packet_type, self.packet_type.status),
+            MultiReg(packet_decoder.write_ptr, self.write_pointer.status),
         ]
 
         # DEBUG: remove this cdc fifo
@@ -240,11 +248,12 @@ class DownConn_Interface(Module, AutoCSR):
         self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
         self.submodules.debug_out = debug_out = RX_Debug_Buffer()
 
-        # TODO: move the rx pipeline to cxp_gtx_rx clockdomain
+
         rx_pipeline = [phy, trig_ack_checker, packet_decoder, cdc_fifo, debug_out]
         for s, d in zip(rx_pipeline, rx_pipeline[1:]):
             self.comb += s.source.connect(d.sink)
         
+
         # DEBUG: CSR
         self.trigger_ack = CSR()
         self.sync += [
@@ -258,6 +267,8 @@ class DownConn_Interface(Module, AutoCSR):
         ]
 
         self.specials += [
+            Instance("OBUF", i_I=phy.gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
+            # Instance("OBUF", i_I=, o_O=debug_sma.p_rx),
             # # pmod 0-7 pin
             Instance("OBUF", i_I=packet_decoder.test_err, o_O=pmod_pads[0]),
             Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),