forked from M-Labs/artiq-zynq
upconn GW: use pipeline upconn layout var
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790f0196b6
commit
cb0a0358a3
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@ -7,6 +7,8 @@ from misoc.cores.code_8b10b import SingleEncoder
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from misoc.interconnect import stream
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from misoc.interconnect import stream
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr import *
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from cxp_pipeline import upconn_layout
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IDLE_CHARS = Array([
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IDLE_CHARS = Array([
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#[char, k]
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#[char, k]
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[0xBC, 1], #K28.5
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[0xBC, 1], #K28.5
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@ -292,7 +294,7 @@ class Debug_buffer(Module,AutoCSR):
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class CXP_UpConn_PHY(Module, AutoCSR):
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class CXP_UpConn_PHY(Module, AutoCSR):
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def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, layout, nsink=3):
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def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, nsink=3):
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self.bitrate2x_enable = Signal()
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self.bitrate2x_enable = Signal()
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self.clk_reset = Signal()
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self.clk_reset = Signal()
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@ -302,12 +304,12 @@ class CXP_UpConn_PHY(Module, AutoCSR):
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# # #
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# # #
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self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
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self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
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self.submodules.interface = interface = PHY_Interface(layout, nsink)
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self.submodules.interface = interface = PHY_Interface(upconn_layout, nsink)
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self.sinks = interface.sinks
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self.sinks = interface.sinks
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# DEBUG:
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# DEBUG:
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self.submodules.debug_buf = debug_buf = Debug_buffer(layout)
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self.submodules.debug_buf = debug_buf = Debug_buffer(upconn_layout)
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self.submodules.scheduler = scheduler = Transmit_Scheduler(interface, debug_buf)
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self.submodules.scheduler = scheduler = Transmit_Scheduler(interface, debug_buf)
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self.submodules.serdes = serdes = SERDES_10bits(pad)
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self.submodules.serdes = serdes = SERDES_10bits(pad)
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@ -346,8 +348,8 @@ class CXP_UpConn_PHY(Module, AutoCSR):
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]
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]
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self.specials += [
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self.specials += [
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# # debug sma
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# # debug sma
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# Instance("OBUF", i_I=cg.clk, o_O=debug_sma.p_tx),
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Instance("OBUF", i_I=serdes.o, o_O=debug_sma.p_tx),
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# Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx),
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Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx),
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