From cb0a0358a300e5c347f654a35948619e696d2412 Mon Sep 17 00:00:00 2001 From: morgan Date: Thu, 12 Sep 2024 13:04:38 +0800 Subject: [PATCH] upconn GW: use pipeline upconn layout var --- src/gateware/cxp_upconn.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/gateware/cxp_upconn.py b/src/gateware/cxp_upconn.py index 1495020..922533f 100644 --- a/src/gateware/cxp_upconn.py +++ b/src/gateware/cxp_upconn.py @@ -7,6 +7,8 @@ from misoc.cores.code_8b10b import SingleEncoder from misoc.interconnect import stream from misoc.interconnect.csr import * +from cxp_pipeline import upconn_layout + IDLE_CHARS = Array([ #[char, k] [0xBC, 1], #K28.5 @@ -292,7 +294,7 @@ class Debug_buffer(Module,AutoCSR): class CXP_UpConn_PHY(Module, AutoCSR): - def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, layout, nsink=3): + def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, nsink=3): self.bitrate2x_enable = Signal() self.clk_reset = Signal() @@ -302,12 +304,12 @@ class CXP_UpConn_PHY(Module, AutoCSR): # # # self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq) - self.submodules.interface = interface = PHY_Interface(layout, nsink) + self.submodules.interface = interface = PHY_Interface(upconn_layout, nsink) self.sinks = interface.sinks # DEBUG: - self.submodules.debug_buf = debug_buf = Debug_buffer(layout) + self.submodules.debug_buf = debug_buf = Debug_buffer(upconn_layout) self.submodules.scheduler = scheduler = Transmit_Scheduler(interface, debug_buf) self.submodules.serdes = serdes = SERDES_10bits(pad) @@ -346,8 +348,8 @@ class CXP_UpConn_PHY(Module, AutoCSR): ] self.specials += [ # # debug sma - # Instance("OBUF", i_I=cg.clk, o_O=debug_sma.p_tx), - # Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx), + Instance("OBUF", i_I=serdes.o, o_O=debug_sma.p_tx), + Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx),