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cxp GW: add eop marker at rx pipeline

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morgan 2025-01-14 10:45:13 +08:00
parent c5d71f269d
commit ca3f6e4bba
1 changed files with 6 additions and 3 deletions
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9
src/gateware/cxp.py
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@ -122,8 +122,8 @@ class DownConn_Interface(Module, AutoCSR):
# Receiver Pipeline WIP
#
# 32 32+8(dchar)
# PHY ---/---> dchar -----/-----> trigger ack ------> packet ------> CDC FIFO ------> raw stream data packet without
# decoder checker decoder the first 2 words (K27.7 & 0x01)
# PHY ---/---> dchar -----/-----> trigger ack ------> packet ------> EOP Marker ------> stream data packet
# decoder checker decoder with CRC
#
cdr = ClockDomainsRenamer("cxp_gtx_rx")
@ -220,8 +220,11 @@ class DownConn_Interface(Module, AutoCSR):
# cdc_fifo = stream.AsyncFIFO(word_layout_dchar, 512)
# self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
# self.submodules.debug_out = debug_out = RX_Debug_Buffer(word_layout_dchar)
# Drop the K29.7 and mark the EOP for arbiter and crc cheker
self.submodules.eop_marker = eop_marker = cdr(EOP_Marker())
rx_pipeline = [phy, dchar_decoder, trig_ack_checker, bootstrap]
rx_pipeline = [phy, dchar_decoder, trig_ack_checker, bootstrap, eop_marker]
for s, d in zip(rx_pipeline, rx_pipeline[1:]):
self.comb += s.source.connect(d.sink)
self.source = rx_pipeline[-1].source