forked from M-Labs/artiq-zynq
downconn GW: add tx&rx packet for debug
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dddea53d26
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ca32914917
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@ -4,8 +4,10 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.cores.code_8b10b import Encoder, Decoder
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from misoc.cores.code_8b10b import Encoder, Decoder
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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from cxp_pipeline import downconn_layout
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from functools import reduce
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from functools import reduce
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from operator import add
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from operator import add
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@ -45,7 +47,6 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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# TODO: add extension gtx connections
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# TODO: add extension gtx connections
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# TODO: add connection interface
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# TODO: add connection interface
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# TODO: Connect slave cxp_gtx_rx clock tgt
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# TODO: Connect slave cxp_gtx_rx clock tgt
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# checkout channel interfaces & drtio_gtx
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# checkout channel interfaces & drtio_gtx
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@ -99,9 +100,35 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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),
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),
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]
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]
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self.sources = []
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for n, gtx in enumerate(self.gtxs):
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# gtx rx -> fifo out -> cdc out
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fifo_out = stream.SyncFIFO(downconn_layout, 128)
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self.submodules += ClockDomainsRenamer("cxp_gtx_rx")(fifo_out)
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cdc_out = stream.AsyncFIFO(downconn_layout, 128)
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self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_out)
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self.sources.append(cdc_out)
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self.comb += fifo_out.source.connect(cdc_out.sink)
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for i in range(4):
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self.sync.cxp_gtx_rx += [
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fifo_out.sink.stb.eq(0),
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# don't store idle word in fifo
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If(gtx.rx_ready & fifo_out.sink.ack & (gtx.decoders[0].d != 0xBC),
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fifo_out.sink.stb.eq(1),
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fifo_out.sink.data[i*8:(i*8)+8].eq(gtx.decoders[i].d),
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fifo_out.sink.k[i].eq(gtx.decoders[i].k),
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),
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]
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# DEBUG: tx of gtx is not used in CXP
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# DEBUG: txusrclk PLL DRG
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# DEBUG: txusrclk PLL DRG
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self.txpll_reset = CSRStorage()
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self.txpll_reset = CSRStorage()
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@ -118,6 +145,9 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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self.txinit_phaligndone = CSRStatus()
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self.txinit_phaligndone = CSRStatus()
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self.rxinit_phaligndone = CSRStatus()
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self.rxinit_phaligndone = CSRStatus()
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self.tx_stb = CSRStorage()
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self.sinks = []
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for n, gtx in enumerate(self.gtxs):
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for n, gtx in enumerate(self.gtxs):
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self.comb += [
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self.comb += [
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gtx.txpll_reset.eq(self.txpll_reset.storage),
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gtx.txpll_reset.eq(self.txpll_reset.storage),
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@ -137,6 +167,47 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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self.loopback_mode = CSRStorage(3)
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self.loopback_mode = CSRStorage(3)
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self.comb += gtx.loopback_mode.eq(self.loopback_mode.storage)
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self.comb += gtx.loopback_mode.eq(self.loopback_mode.storage)
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# DEBUG: datain
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# fw -> fifo (sys) -> cdc fifo -> fifo in -> gtx tx
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fifo_in = stream.AsyncFIFO(downconn_layout, 128)
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self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(fifo_in)
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self.sinks.append(fifo_in)
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# TODO: why there this send an extra 0xFB word
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txstb = Signal()
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self.specials += MultiReg(self.tx_stb.storage, txstb, odomain="cxp_gtx_tx")
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self.sync.cxp_gtx_tx += [
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fifo_in.source.ack.eq(0),
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If(fifo_in.source.stb & txstb,
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fifo_in.source.ack.eq(1),
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)
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]
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self.comb += [
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If(fifo_in.source.stb & fifo_in.source.ack,
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gtx.encoder.d[0].eq(fifo_in.source.data[:8]),
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gtx.encoder.d[1].eq(fifo_in.source.data[8:16]),
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gtx.encoder.d[2].eq(fifo_in.source.data[16:24]),
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gtx.encoder.d[3].eq(fifo_in.source.data[24:]),
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gtx.encoder.k[0].eq(fifo_in.source.k[0]),
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gtx.encoder.k[1].eq(fifo_in.source.k[1]),
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gtx.encoder.k[2].eq(fifo_in.source.k[2]),
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gtx.encoder.k[3].eq(fifo_in.source.k[3]),
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).Else(
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# NOTE: IDLE WORD
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gtx.encoder.d[0].eq(0xBC),
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gtx.encoder.k[0].eq(1),
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gtx.encoder.d[1].eq(0x3C),
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gtx.encoder.k[1].eq(1),
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gtx.encoder.d[2].eq(0x3C),
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gtx.encoder.k[2].eq(1),
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gtx.encoder.d[3].eq(0xB5),
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gtx.encoder.k[3].eq(0),
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)
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]
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# DEBUG: IO SMA & PMOD
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# DEBUG: IO SMA & PMOD
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if n == 0:
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if n == 0:
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self.specials += [
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self.specials += [
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@ -144,9 +215,9 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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# Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
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# Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
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# # pmod 0-7 pin
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# # pmod 0-7 pin
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# Instance("OBUF", i_I=gtx.comma_checker.comma_aligned, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=txstb, o_O=pmod_pads[0]),
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# Instance("OBUF", i_I=gtx.comma_checker.comma_det, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=fifo_in.source.stb, o_O=pmod_pads[1]),
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# Instance("OBUF", i_I=gtx.comma_checker.restart_sys, o_O=pmod_pads[2]),
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Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
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# Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
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# Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
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# Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),
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# Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),
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# Instance("OBUF", i_I=gtx.comma_checker.has_comma, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=gtx.comma_checker.has_comma, o_O=pmod_pads[5]),
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@ -159,43 +230,6 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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# Instance("OBUF", i_I=gtx.dready, o_O=pmod_pads[3]),
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# Instance("OBUF", i_I=gtx.dready, o_O=pmod_pads[3]),
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]
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]
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# DEBUG: datain
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self.sync.cxp_gtx_tx += [
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gtx.encoder.d[0].eq(0xBC),
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gtx.encoder.k[0].eq(1),
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gtx.encoder.d[1].eq(0x3C),
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gtx.encoder.k[1].eq(1),
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gtx.encoder.d[2].eq(0x3C),
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gtx.encoder.k[2].eq(1),
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gtx.encoder.d[3].eq(0xB5),
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gtx.encoder.k[3].eq(0),
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]
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for i in range(4):
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gtx.decoders[i].input.attr.add("no_retiming")
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gtx.decoders[i].d.attr.add("no_retiming")
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gtx.decoders[i].k.attr.add("no_retiming")
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rxdata_name = "rxdata_" + str(i)
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rxdata_csr = CSRStatus(10, name=rxdata_name)
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setattr(self, rxdata_name, rxdata_csr)
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decoded_name = "decoded_data_" + str(i)
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decoded_csr = CSRStatus(8, name=decoded_name)
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setattr(self, decoded_name, decoded_csr)
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k_name = "rxdata_" + str(i)
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k_csr = CSRStatus(1, name=k_name)
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setattr(self, k_name, k_csr)
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self.sync.cxp_gtx_rx += [
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rxdata_csr.status.eq(gtx.decoders[i].input),
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decoded_csr.status.eq(gtx.decoders[i].d),
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k_csr.status.eq(gtx.decoders[i].k),
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]
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class QPLL(Module, AutoCSR):
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class QPLL(Module, AutoCSR):
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def __init__(self, refclk, sys_clk_freq):
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def __init__(self, refclk, sys_clk_freq):
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self.clk = Signal()
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self.clk = Signal()
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