forked from M-Labs/artiq-zynq
temp diagrams & unused sim
This commit is contained in:
parent
2d52bab14a
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38
build_CI.sh
Executable file
38
build_CI.sh
Executable file
@ -0,0 +1,38 @@
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#!/usr/bin/env bash
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set -e
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if [ -z "$OPENOCD_ZYNQ" ]; then
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echo "OPENOCD_ZYNQ environment variable must be set"
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exit 1
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fi
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if [ -z "$SZL" ]; then
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echo "SZL environment variable must be set"
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exit 1
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fi
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# variant="firmware"
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# variant="gateware"
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# variant="jtag"
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variant="sd"
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nix build .#kasli_soc-demo-$variant -L
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nix build .#kasli_soc-master-$variant -L
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nix build .#kasli_soc-satellite-$variant -L
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# nix build .#zc706-acpki_nist_clock-$variant -L
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# nix build .#zc706-acpki_nist_clock_master-$variant -L
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# nix build .#zc706-acpki_nist_clock_satellite-$variant -L
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# nix build .#zc706-acpki_nist_qc2-$variant -L
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# nix build .#zc706-acpki_nist_qc2_master-$variant -L
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# nix build .#zc706-acpki_nist_qc2_satellite-$variant -L
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# nix build .#zc706-nist_clock-$variant -L
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# nix build .#zc706-nist_clock_master-$variant -L
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# nix build .#zc706-nist_clock_satellite-$variant -L
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# nix build .#zc706-nist_qc2-$variant -L
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# nix build .#zc706-nist_qc2_master-$variant -L
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# nix build .#zc706-nist_qc2_satellite-$variant -L
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5
cargofmt.sh
Executable file
5
cargofmt.sh
Executable file
@ -0,0 +1,5 @@
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#!/usr/bin/env bash
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nix-shell -p gnumake --command 'make manifests -B'
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cd src
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cargo fmt -- --check
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338
coaxpress.drawio
Normal file
338
coaxpress.drawio
Normal file
@ -0,0 +1,338 @@
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<mxfile host="65bd71144e">
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<diagram id="en7HUHNV3kVsTTCxeEt8" name="Page-1">
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<mxGraphModel dx="1155" dy="1481" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="0" pageScale="1" pageWidth="850" pageHeight="1100" background="none" math="0" shadow="0">
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<root>
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<mxCell id="0"/>
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<mxCell id="1" parent="0"/>
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<mxCell id="21" value="TX<br style="border-color: var(--border-color);">Low speed" style="shape=offPageConnector;whiteSpace=wrap;html=1;rotation=0;size=0.3333333333333333;direction=south;fillColor=#DAE8FC;strokeColor=#6c8ebf;rounded=0;" parent="1" vertex="1">
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</mxCell>
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<mxCell id="24" value="RX GTX<br style="border-color: var(--border-color);">High Speed<br>Master" style="shape=offPageConnector;whiteSpace=wrap;html=1;rotation=0;size=0.3333333333333333;direction=north;fillColor=#f8cecc;strokeColor=#b85450;rounded=0;" parent="1" vertex="1">
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<mxGeometry x="120" y="240" width="120" height="80" as="geometry"/>
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</mxCell>
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<mxCell id="25" value="TX High Speed<br>(optional)" style="shape=offPageConnector;whiteSpace=wrap;html=1;rotation=0;size=0.3333333333333333;direction=south;fillColor=#f8cecc;strokeColor=#b85450;dashed=1;rounded=0;" parent="1" vertex="1">
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<mxGeometry x="120" y="560" width="120" height="80" as="geometry"/>
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</mxCell>
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<mxCell id="26" value="RX GTX<br style="border-color: var(--border-color);">High Speed&nbsp;<br>Extension<br>(Optional)" style="shape=offPageConnector;whiteSpace=wrap;html=1;rotation=0;size=0.4166666666666667;direction=north;fillColor=#f8cecc;strokeColor=#b85450;rounded=0;dashed=1;" parent="1" vertex="1">
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<mxGeometry x="120" width="120" height="80" as="geometry"/>
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<mxCell id="30" value="" style="endArrow=classic;html=1;entryX=1;entryY=0.5;entryDx=0;entryDy=0;rounded=0;" parent="1" edge="1">
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<mxGeometry x="-0.375" y="4" relative="1" as="geometry">
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</mxCell>
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<mxCell id="33" value="<div style="text-align: justify;"><span style="background-color: initial;">TX pipeline</span></div><div style="text-align: justify;"><span style="background-color: initial;">- priority transmission</span></div><div style="text-align: justify;"><span style="background-color: initial;">- IDLE</span></div>" style="rounded=0;whiteSpace=wrap;html=1;align=center;" parent="1" vertex="1">
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<mxCell id="38" value="Red: clocked by cxp_gtx_rx/tx (31.25MHz - 312.5MHz)&nbsp;" style="rounded=0;whiteSpace=wrap;html=1;labelBackgroundColor=none;strokeColor=#b85450;fillColor=#f8cecc;align=left;" parent="1" vertex="1">
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<mxGeometry x="120" y="680" width="360" height="40" as="geometry"/>
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</mxCell>
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<mxCell id="39" value="Blue: clocked by sys with CEInserter (20.83MHz - 41.66MHz)&nbsp;" style="rounded=0;whiteSpace=wrap;html=1;labelBackgroundColor=none;strokeColor=#6c8ebf;fillColor=#dae8fc;align=left;" parent="1" vertex="1">
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<mxGeometry x="120" y="720" width="360" height="40" as="geometry"/>
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</mxCell>
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<mxCell id="40" value="White: clocked by sys (125MHz)" style="rounded=0;whiteSpace=wrap;html=1;labelBackgroundColor=none;strokeColor=default;fontColor=#000000;fillColor=default;align=left;" parent="1" vertex="1">
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<mxGeometry x="120" y="800" width="360" height="40" as="geometry"/>
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</mxCell>
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<mxCell id="43" value="<div style="text-align: justify;"><span style="background-color: initial;"><b><u>CXP Bootstrap FW</u></b></span></div><div style="text-align: justify;"><span style="background-color: initial;">- handle GTX speed</span></div><div style="text-align: justify;"><span style="background-color: initial;">- test connection</span></div><div style="text-align: justify;"><span style="background-color: initial;">- hand over to RTIO after init</span></div><div style="text-align: justify;"><span style="background-color: initial;"><span style="white-space: pre;">	</span>- cannot access CTRL PAK</span></div><div style="text-align: justify;"><span style="background-color: initial;">- with camera specific .rs file</span></div><div style="text-align: justify;"><span style="background-color: initial;">- compare heatbeat to check connection status</span></div><div style="text-align: justify;"><span style="background-color: initial;">- handle event ack??</span></div><div style="text-align: justify;"><span style="background-color: initial;">- don't use tag?</span></div>" style="rounded=0;whiteSpace=wrap;html=1;align=center;fillColor=#fff2cc;strokeColor=#d6b656;" parent="1" vertex="1">
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<mxGeometry x="800" y="240" width="240" height="240" as="geometry"/>
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||||
</mxCell>
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<mxCell id="53" value="<div style="text-align: justify;"><span style="background-color: initial;"><u><b>CXP Camera specific prog</b></u><br>GenICam interface @&nbsp;</span></div><div style="text-align: justify;"><span style="background-color: initial;">RTIO coredevice</span></div><div style="text-align: justify;"><span style="background-color: initial;">- handle frame programming</span></div><div style="text-align: justify;"><span style="background-color: initial;">- handle event as well??</span></div><div style="text-align: justify;"><span style="background-color: initial;">- two interface</span></div><div style="text-align: justify;"><span style="background-color: initial;">&nbsp; &nbsp;- IO CTRL packet via API!</span></div><div style="text-align: justify;"><span style="background-color: initial;">&nbsp; &nbsp;- on master ch only</span></div><div style="text-align: justify;"><span style="background-color: initial;">&nbsp; &nbsp;- O Frame data</span></div>" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#d5e8d4;strokeColor=#82b366;" parent="1" vertex="1">
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<mxGeometry x="1120" y="80" width="160" height="480" as="geometry"/>
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||||
</mxCell>
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<mxCell id="54" value="RX pipeline" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" parent="1" vertex="1">
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<mxGeometry x="400" width="160" height="80" as="geometry"/>
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</mxCell>
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|
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|
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<mxCell id="71" value="<div style="text-align: justify;"><span style="background-color: initial;">TX Bootstrap</span></div><div style="text-align: justify;"><span style="background-color: initial;">- testseq</span><br></div><div style="text-align: justify;"><span style="background-color: initial;">- DMA</span></div>" style="rounded=0;whiteSpace=wrap;html=1;align=center;" parent="1" vertex="1">
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||||
<mxGeometry x="640" y="400" width="80" height="80" as="geometry"/>
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|
||||
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|
||||
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|
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|
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|
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<mxGeometry x="-0.5034" y="1" relative="1" as="geometry">
|
||||
<mxPoint x="20" y="-9" as="offset"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="180" value="Streams<br>Crossbar" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" parent="1" vertex="1">
|
||||
<mxGeometry x="760" y="-480" width="80" height="320" as="geometry"/>
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||||
</mxCell>
|
||||
<mxCell id="181" value="ROI Engine" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#d5e8d4;strokeColor=#82b366;" parent="1" vertex="1">
|
||||
<mxGeometry x="1560" y="-360" width="80" height="80" as="geometry"/>
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</mxCell>
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||||
<mxCell id="182" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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<mxGeometry width="100" relative="1" as="geometry">
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<mxPoint x="1480" y="-320.0000000000001" as="sourcePoint"/>
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<mxPoint x="1560" y="-319.62" as="targetPoint"/>
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<Array as="points"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="185" value="<div style=""><span style="background-color: initial;">- 32bit pixel data</span></div>- frame valid (new frame)<br>- line break" style="text;html=1;align=left;verticalAlign=middle;resizable=0;points=[];autosize=1;strokeColor=none;fillColor=none;" parent="1" vertex="1">
|
||||
<mxGeometry x="1520" y="-430" width="160" height="60" as="geometry"/>
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</mxCell>
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||||
<mxCell id="186" value="CRC Checker" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" parent="1" vertex="1">
|
||||
<mxGeometry x="920" y="-360.42" width="80" height="80" as="geometry"/>
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</mxCell>
|
||||
<mxCell id="187" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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<mxGeometry width="100" relative="1" as="geometry">
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<mxPoint x="1000" y="-321.25000000000017" as="sourcePoint"/>
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<mxPoint x="1080" y="-320.87000000000006" as="targetPoint"/>
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<Array as="points"/>
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</mxGeometry>
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</mxCell>
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<mxCell id="188" value="Double<br>Buffered<br>Memory" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" parent="1" vertex="1">
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<mxGeometry x="1080" y="-360.42" width="80" height="80" as="geometry"/>
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</mxCell>
|
||||
<mxCell id="194" value="Pixel Decoder" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#fad9d5;strokeColor=#ae4132;" parent="1" vertex="1">
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<mxGeometry x="1400" y="-360" width="80" height="80" as="geometry"/>
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</mxCell>
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||||
<mxCell id="195" value="<div style=""><span style="background-color: initial;">- extract line break &amp; new frame</span></div>" style="text;html=1;align=left;verticalAlign=middle;resizable=0;points=[];autosize=1;strokeColor=none;fillColor=none;" parent="1" vertex="1">
|
||||
<mxGeometry x="1400" y="-270" width="190" height="30" as="geometry"/>
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</mxCell>
|
||||
<mxCell id="203" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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<mxGeometry width="100" relative="1" as="geometry">
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<mxPoint x="1160" y="-319.9999999999999" as="sourcePoint"/>
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<mxPoint x="1240" y="-319.6199999999998" as="targetPoint"/>
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<Array as="points"/>
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</mxGeometry>
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</mxCell>
|
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<mxCell id="205" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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<mxGeometry width="100" relative="1" as="geometry">
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<mxPoint x="840" y="-320.4200000000002" as="sourcePoint"/>
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<mxPoint x="920" y="-320.0400000000001" as="targetPoint"/>
|
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<Array as="points"/>
|
||||
</mxGeometry>
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||||
</mxCell>
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||||
<mxCell id="206" value="CRC Checker" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;dashed=1;" parent="1" vertex="1">
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<mxGeometry x="920" y="-480" width="80" height="80" as="geometry"/>
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</mxCell>
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<mxCell id="207" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;dashed=1;" parent="1" edge="1">
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<mxGeometry width="100" relative="1" as="geometry">
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<mxPoint x="1000" y="-440.83000000000027" as="sourcePoint"/>
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<mxPoint x="1080" y="-440.45000000000016" as="targetPoint"/>
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<Array as="points"/>
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</mxCell>
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<mxCell id="208" value="Double<br>Buffered<br>Memory" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;dashed=1;" parent="1" vertex="1">
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<mxGeometry x="1080" y="-480" width="80" height="80" as="geometry"/>
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</mxCell>
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<mxCell id="209" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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<mxGeometry width="100" relative="1" as="geometry">
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<mxPoint x="680" y="-440.4200000000003" as="sourcePoint"/>
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<Array as="points"/>
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</mxGeometry>
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<mxCell id="210" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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<mxPoint x="680" y="-280.00000000000017" as="sourcePoint"/>
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<Array as="points"/>
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</mxGeometry>
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</mxCell>
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<mxCell id="211" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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<mxGeometry width="100" relative="1" as="geometry">
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<mxPoint x="680" y="-360.00000000000017" as="sourcePoint"/>
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<Array as="points"/>
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</mxGeometry>
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</mxCell>
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||||
<mxCell id="212" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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<mxGeometry width="100" relative="1" as="geometry">
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<mxPoint x="680" y="-200.49000000000018" as="sourcePoint"/>
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<mxPoint x="760" y="-200.11000000000007" as="targetPoint"/>
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<Array as="points"/>
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</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="213" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;dashed=1;" parent="1" edge="1">
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<mxGeometry width="100" relative="1" as="geometry">
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<mxPoint x="840" y="-440.42000000000036" as="sourcePoint"/>
|
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<mxPoint x="920" y="-440.04000000000025" as="targetPoint"/>
|
||||
<Array as="points"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="214" value="Stream<br>Parser" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" parent="1" vertex="1">
|
||||
<mxGeometry x="1240" y="-360.00000000000006" width="80" height="80" as="geometry"/>
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||||
</mxCell>
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||||
<mxCell id="215" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
|
||||
<mxGeometry width="100" relative="1" as="geometry">
|
||||
<mxPoint x="1320" y="-320.41999999999996" as="sourcePoint"/>
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||||
<mxPoint x="1400" y="-320.03999999999985" as="targetPoint"/>
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||||
<Array as="points"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="216" value="Streams<br>Crossbar" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" vertex="1" parent="1">
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||||
<mxGeometry x="800" y="-40" width="80" height="200" as="geometry"/>
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||||
</mxCell>
|
||||
<mxCell id="217" value="Stream pipeline #1" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" vertex="1" parent="1">
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||||
<mxGeometry x="960" y="80" width="80" height="80" as="geometry"/>
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||||
</mxCell>
|
||||
<mxCell id="218" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" edge="1" parent="1">
|
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<mxGeometry width="100" relative="1" as="geometry">
|
||||
<mxPoint x="880" y="119.57999999999993" as="sourcePoint"/>
|
||||
<mxPoint x="960" y="119.96000000000004" as="targetPoint"/>
|
||||
<Array as="points"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
</root>
|
||||
</mxGraphModel>
|
||||
</diagram>
|
||||
</mxfile>
|
||||
57
cxp_note.md
Normal file
57
cxp_note.md
Normal file
@ -0,0 +1,57 @@
|
||||
# CXP
|
||||
|
||||
## Finished
|
||||
- Upconn - Low speed serial
|
||||
[x] Low speed serial PHY
|
||||
[x] 20.833Mbps & 41.666Mbps change
|
||||
[x] 8b10b encoder
|
||||
[x] TX Pipeline with priority transmission
|
||||
[x] Trigger
|
||||
[x] Trigger ack
|
||||
[x] Test & Ctrl packet with DMA
|
||||
[x] CTRL Packet serialize firmware
|
||||
[x] follow DRTIO DMA
|
||||
[x] check crc
|
||||
- Downconn - GTX
|
||||
[x] GTX serial PHY
|
||||
[x] QPLL & GTX DRP to config linerate
|
||||
[x] Comma checker & restart rx
|
||||
[x] RX Pipeline with priority decoder
|
||||
[x] Trigger ack
|
||||
[x] CTRL packet DMA with extra buffer
|
||||
[x] Connection test sequence checker
|
||||
[x] CTRL Packet deserialize firmware
|
||||
[x] follow DRTIO DMA
|
||||
[x] check crc
|
||||
- Camera boostrap
|
||||
|
||||
## TODO
|
||||
[] remove ALL debug tools
|
||||
[] flake.nix mod
|
||||
[] local_run.sh mod
|
||||
### Gateware
|
||||
[] GTX Multilane setup
|
||||
[] Region of interest engine
|
||||
[] rtio to getting the frame
|
||||
- O: trigger
|
||||
- I: frame
|
||||
- frame crc checker
|
||||
|
||||
### Firmware
|
||||
[] Camera boostrap
|
||||
- get the CXP version
|
||||
- test connection
|
||||
- discovery other extension (links)
|
||||
- set bitrate
|
||||
[] Camera linkdown detection
|
||||
[] API programming
|
||||
[] add tag handling for api calls
|
||||
- support line reset in kernel using syscall
|
||||
[] add heartbeat checking
|
||||
|
||||
### Coredevice Driver
|
||||
[] support simple GenICam api
|
||||
- camera specific register that hold the same value between reset
|
||||
- support sub-array readout (i.e Region of Interest (ROI))
|
||||
|
||||
|
||||
20
flake.lock
generated
20
flake.lock
generated
@ -11,11 +11,11 @@
|
||||
"src-pythonparser": "src-pythonparser"
|
||||
},
|
||||
"locked": {
|
||||
"lastModified": 1732066716,
|
||||
"narHash": "sha256-krjvt9+RccnAxSEZcFhRpjA2S3CoqE4MSa1JUg421b4=",
|
||||
"lastModified": 1725373154,
|
||||
"narHash": "sha256-fq9EW9fDWrV0v1vNj7ZqDNpNYx8+OxoFdPwpvkPf67g=",
|
||||
"ref": "refs/heads/master",
|
||||
"rev": "270a417a28b516d36983779a1adb6d33a3c55a4a",
|
||||
"revCount": 9102,
|
||||
"rev": "0c1ffa9f4f6a3e7864459923ec4b9cc45f16327a",
|
||||
"revCount": 9005,
|
||||
"type": "git",
|
||||
"url": "https://github.com/m-labs/artiq.git"
|
||||
},
|
||||
@ -70,11 +70,11 @@
|
||||
},
|
||||
"nixpkgs": {
|
||||
"locked": {
|
||||
"lastModified": 1731319897,
|
||||
"narHash": "sha256-PbABj4tnbWFMfBp6OcUK5iGy1QY+/Z96ZcLpooIbuEI=",
|
||||
"lastModified": 1724224976,
|
||||
"narHash": "sha256-Z/ELQhrSd7bMzTO8r7NZgi9g5emh+aRKoCdaAv5fiO0=",
|
||||
"owner": "NixOS",
|
||||
"repo": "nixpkgs",
|
||||
"rev": "dc460ec76cbff0e66e269457d7b728432263166c",
|
||||
"rev": "c374d94f1536013ca8e92341b540eba4c22f9c62",
|
||||
"type": "github"
|
||||
},
|
||||
"original": {
|
||||
@ -175,11 +175,11 @@
|
||||
"src-migen": {
|
||||
"flake": false,
|
||||
"locked": {
|
||||
"lastModified": 1727677091,
|
||||
"narHash": "sha256-Zg3SQnTwMM/VkOGKogbPyuCC2NhLy8HB2SPEUWWNgCU=",
|
||||
"lastModified": 1724304798,
|
||||
"narHash": "sha256-tQ02N0eXY5W/Z7CrOy3Cu4WjDZDQWb8hYlzsFzr3Mus=",
|
||||
"owner": "m-labs",
|
||||
"repo": "migen",
|
||||
"rev": "c19ae9f8ae162ffe2d310a92bfce53ac2a821bc8",
|
||||
"rev": "832a7240ba32af9cbd4fdd519ddcb4f912534726",
|
||||
"type": "github"
|
||||
},
|
||||
"original": {
|
||||
|
||||
82
notes.drawio
Normal file
82
notes.drawio
Normal file
@ -0,0 +1,82 @@
|
||||
<mxfile host="65bd71144e">
|
||||
<diagram id="en7HUHNV3kVsTTCxeEt8" name="Page-1">
|
||||
<mxGraphModel dx="924" dy="545" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="0" pageScale="1" pageWidth="850" pageHeight="1100" background="none" math="0" shadow="0">
|
||||
<root>
|
||||
<mxCell id="0"/>
|
||||
<mxCell id="1" parent="0"/>
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||||
<mxCell id="50" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
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||||
<mxGeometry width="50" height="50" relative="1" as="geometry">
|
||||
<mxPoint x="280" y="200" as="sourcePoint"/>
|
||||
<mxPoint x="440" y="200" as="targetPoint"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="52" value="Payload (layout)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="50">
|
||||
<mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
|
||||
<mxPoint x="-63" as="offset"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="53" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
|
||||
<mxGeometry width="50" height="50" relative="1" as="geometry">
|
||||
<mxPoint x="280" y="239.81" as="sourcePoint"/>
|
||||
<mxPoint x="440" y="239.81" as="targetPoint"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="54" value="stb (valid/readable)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="53">
|
||||
<mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
|
||||
<mxPoint x="-63" y="-1" as="offset"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="55" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
|
||||
<mxGeometry width="50" height="50" relative="1" as="geometry">
|
||||
<mxPoint x="440" y="279.80999999999995" as="sourcePoint"/>
|
||||
<mxPoint x="280" y="279.80999999999995" as="targetPoint"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="56" value="ack (ready)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="55">
|
||||
<mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
|
||||
<mxPoint x="-197" y="1" as="offset"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="48" value="Source" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#d5e8d4;strokeColor=#82b366;" vertex="1" parent="1">
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||||
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||||
</mxCell>
|
||||
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||||
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|
||||
<mxPoint x="520" y="200" as="sourcePoint"/>
|
||||
<mxPoint x="680" y="200" as="targetPoint"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="58" value="Payload (layout)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="57">
|
||||
<mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
|
||||
<mxPoint x="197" as="offset"/>
|
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</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="59" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
|
||||
<mxGeometry width="50" height="50" relative="1" as="geometry">
|
||||
<mxPoint x="520" y="239.80999999999995" as="sourcePoint"/>
|
||||
<mxPoint x="680" y="239.80999999999995" as="targetPoint"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="60" value="stb (valid)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="59">
|
||||
<mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
|
||||
<mxPoint x="197" y="-1" as="offset"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="61" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
|
||||
<mxGeometry width="50" height="50" relative="1" as="geometry">
|
||||
<mxPoint x="680" y="279.99999999999994" as="sourcePoint"/>
|
||||
<mxPoint x="520" y="279.99999999999994" as="targetPoint"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="62" value="ack (ready/writeable)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="61">
|
||||
<mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
|
||||
<mxPoint x="73" y="1" as="offset"/>
|
||||
</mxGeometry>
|
||||
</mxCell>
|
||||
<mxCell id="49" value="Sink" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#ffe6cc;strokeColor=#d79b00;" vertex="1" parent="1">
|
||||
<mxGeometry x="560" y="160" width="80" height="160" as="geometry"/>
|
||||
</mxCell>
|
||||
</root>
|
||||
</mxGraphModel>
|
||||
</diagram>
|
||||
</mxfile>
|
||||
17
reset.py
Normal file
17
reset.py
Normal file
@ -0,0 +1,17 @@
|
||||
from time import sleep
|
||||
from pyftdi.ftdi import Ftdi
|
||||
|
||||
POR = 1 << 7
|
||||
|
||||
def main():
|
||||
dev = Ftdi()
|
||||
dev.open_bitbang_from_url("ftdi://ftdi:4232h/0")
|
||||
dev.set_bitmode(POR, Ftdi.BitMode.BITBANG)
|
||||
dev.write_data(bytes([0]))
|
||||
sleep(0.1)
|
||||
dev.write_data(bytes([POR]))
|
||||
sleep(0.1)
|
||||
dev.close()
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
63
sat_run.sh
Executable file
63
sat_run.sh
Executable file
@ -0,0 +1,63 @@
|
||||
#!/usr/bin/env bash
|
||||
|
||||
python reset.py
|
||||
|
||||
set -e
|
||||
|
||||
if [ -z "$OPENOCD_ZYNQ" ]; then
|
||||
echo "OPENOCD_ZYNQ environment variable must be set"
|
||||
exit 1
|
||||
fi
|
||||
if [ -z "$SZL" ]; then
|
||||
echo "SZL environment variable must be set"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
impure=0
|
||||
load_bitstream=1
|
||||
board_type="kasli_soc"
|
||||
fw_type="satman"
|
||||
|
||||
while getopts "ilb:t:f:" opt; do
|
||||
case "$opt" in
|
||||
\?) exit 1
|
||||
;;
|
||||
i) impure=1
|
||||
;;
|
||||
l) load_bitstream=0
|
||||
;;
|
||||
b) board_host=$OPTARG
|
||||
;;
|
||||
t) board_type=$OPTARG
|
||||
;;
|
||||
f) fw_type=$OPTARG
|
||||
;;
|
||||
esac
|
||||
done
|
||||
|
||||
if [ -z "$board_host" ]; then
|
||||
case $board_type in
|
||||
kasli_soc) board_host="192.168.1.56";;
|
||||
zc706) board_host="192.168.1.52";;
|
||||
*) echo "Unknown board type"; exit 1;;
|
||||
esac
|
||||
fi
|
||||
|
||||
load_bitstream_cmd=""
|
||||
|
||||
build_dir=`pwd`/build
|
||||
result_dir=`pwd`/result
|
||||
cd $OPENOCD_ZYNQ
|
||||
openocd -f $board_type.cfg -c "load_image $SZL/szl-$board_type.elf; resume 0; exit"
|
||||
sleep 5
|
||||
if [ $impure -eq 1 ]; then
|
||||
if [ $load_bitstream -eq 1 ]; then
|
||||
load_bitstream_cmd="-g $build_dir/gateware/top.bit"
|
||||
fi
|
||||
artiq_netboot $load_bitstream_cmd -f $build_dir/$fw_type.bin -b $board_host
|
||||
else
|
||||
if [ $load_bitstream -eq 1 ]; then
|
||||
load_bitstream_cmd="-g $result_dir/top.bit"
|
||||
fi
|
||||
artiq_netboot $load_bitstream_cmd -f $result_dir/$fw_type.bin -b $board_host
|
||||
fi
|
||||
55
sim.py
Normal file
55
sim.py
Normal file
@ -0,0 +1,55 @@
|
||||
from migen import *
|
||||
from misoc.interconnect.csr import *
|
||||
|
||||
from functools import reduce
|
||||
from itertools import combinations
|
||||
from operator import or_, and_
|
||||
|
||||
class Voter(Module):
|
||||
def __init__(self):
|
||||
self.data_4x = Signal(32)
|
||||
self.k_4x = Signal(4)
|
||||
|
||||
# Section 9.2.2.1 (CXP-001-2021)
|
||||
# decoder should immune to single bit errors when handling duplicated characters
|
||||
self.char = Signal(8)
|
||||
self.k = Signal()
|
||||
|
||||
|
||||
# majority voting
|
||||
char = [[self.data_4x[i*8:(i+1)*8], self.k_4x[i]] for i in range(4)]
|
||||
voter = [Record([("data", 8), ("k", 1)]) for _ in range(4)]
|
||||
|
||||
# stage 1
|
||||
for i, code in enumerate(combinations(char, 3)):
|
||||
self.sync += [
|
||||
voter[i].data.eq(reduce(and_, [c[0] for c in code])),
|
||||
voter[i].k.eq(reduce(and_, [c[1] for c in code])),
|
||||
]
|
||||
|
||||
# stage 2
|
||||
self.sync += [
|
||||
self.char.eq(reduce(or_, [v.data for v in voter])),
|
||||
self.k.eq(reduce(or_, [v.k for v in voter])),
|
||||
]
|
||||
|
||||
|
||||
|
||||
|
||||
dut = Voter()
|
||||
def check_case(data_4x, k_4x, char, k):
|
||||
yield dut.data_4x.eq(data_4x)
|
||||
yield dut.k_4x.eq(k_4x)
|
||||
yield
|
||||
yield
|
||||
yield
|
||||
print(f"char = {yield dut.char:#X} k = {yield dut.k:#X}")
|
||||
assert (yield dut.char) == char and (yield dut.k) == k
|
||||
|
||||
def testbench():
|
||||
yield from check_case(0xFFFFFFFF, 0b1111, 0xFF, 1)
|
||||
yield from check_case(0xFFFFFF00, 0b1110, 0xFF, 1)
|
||||
yield from check_case(0xFFFFF00f, 0b0001, 0xFF, 0)
|
||||
yield from check_case(0xFFFFFFFF, 0b1111, 0xFF, 1)
|
||||
|
||||
run_simulation(dut, testbench())
|
||||
28
sim_comb.py
Normal file
28
sim_comb.py
Normal file
@ -0,0 +1,28 @@
|
||||
from migen import *
|
||||
from misoc.interconnect import stream
|
||||
|
||||
class Frame(Module):
|
||||
def __init__(self):
|
||||
self.a = Signal()
|
||||
self.b = Signal()
|
||||
self.comb += [
|
||||
self.a.eq(self.b),
|
||||
# self.b.eq(self.a),
|
||||
]
|
||||
|
||||
dut = Frame()
|
||||
|
||||
def check_case():
|
||||
yield dut.a.eq(1)
|
||||
yield
|
||||
yield dut.a.eq(0)
|
||||
yield
|
||||
for i in range(10):
|
||||
yield
|
||||
|
||||
|
||||
def testbench():
|
||||
yield from check_case()
|
||||
|
||||
|
||||
run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")
|
||||
58
sim_crc.py
Normal file
58
sim_crc.py
Normal file
@ -0,0 +1,58 @@
|
||||
from migen import *
|
||||
from misoc.interconnect import stream
|
||||
from sim_pipeline import *
|
||||
from src.gateware.cxp_pipeline import *
|
||||
|
||||
dut = StreamData_Generator()
|
||||
|
||||
|
||||
def check_case(packet=[], ack=0):
|
||||
print("=================TEST========================")
|
||||
for i, p in enumerate(packet):
|
||||
yield dut.sink.data.eq(p["data"])
|
||||
yield dut.sink.k.eq(p["k"])
|
||||
yield dut.sink.stb.eq(1)
|
||||
if "eop" in p:
|
||||
yield dut.sink.eop.eq(1)
|
||||
|
||||
# CLK
|
||||
yield
|
||||
|
||||
sink = dut.sink
|
||||
source = dut.source
|
||||
crc = dut.crc_inserter.crc
|
||||
print(
|
||||
# f"\n CYCLE#{i} : sink char = {yield sink.data:#X} k = {yield sink.k:#X}"
|
||||
f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X}"
|
||||
f" stb = {yield source.stb} eop = {yield source.eop} ack = {yield source.ack} "
|
||||
f"\nCYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
|
||||
f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X}"
|
||||
f"\nCYCLE#{i} : crc ce = {yield crc.ce:#X} "
|
||||
)
|
||||
# extra clk cycles
|
||||
cyc = i + 1
|
||||
for i in range(cyc, cyc + 11):
|
||||
# yield has memory for some reason
|
||||
yield dut.sink.stb.eq(0)
|
||||
yield dut.source.ack.eq(1)
|
||||
yield
|
||||
print(
|
||||
# f"\n CYCLE#{i} : sink char = {yield sink.data:#X} k = {yield sink.k:#X}"
|
||||
f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X}"
|
||||
f" stb = {yield source.stb} eop = {yield source.eop} ack = {yield source.ack} "
|
||||
f"\nCYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
|
||||
f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X}"
|
||||
f"\nCYCLE#{i} : crc ce = {yield crc.ce:#X} "
|
||||
)
|
||||
assert True
|
||||
|
||||
|
||||
def testbench():
|
||||
packet = [
|
||||
{"data": 0x0000_0004, "k": Replicate(0, 4)},
|
||||
{"data": 0x0000_0000, "k": Replicate(0, 4), "eop":1},
|
||||
]
|
||||
yield from check_case(packet)
|
||||
|
||||
|
||||
run_simulation(dut, testbench())
|
||||
149
sim_idle.py
Normal file
149
sim_idle.py
Normal file
@ -0,0 +1,149 @@
|
||||
from migen import *
|
||||
from misoc.interconnect import stream
|
||||
|
||||
from src.gateware.cxp_pipeline import Packet_Wrapper
|
||||
|
||||
char_width = 8
|
||||
word_dw = 32
|
||||
word_layout = [("data", word_dw), ("k", word_dw//8)]
|
||||
|
||||
|
||||
def K(x, y):
|
||||
return ((y << 5) | x)
|
||||
|
||||
KCode = {
|
||||
"pak_start" : C(K(27, 7), char_width),
|
||||
"io_ack" : C(K(28, 6), char_width),
|
||||
"trig_indic_28_2" : C(K(28, 2), char_width),
|
||||
"stream_marker" : C(K(28, 3), char_width),
|
||||
"trig_indic_28_4" : C(K(28, 4), char_width),
|
||||
"pak_end" : C(K(29, 7), char_width),
|
||||
"idle_comma" : C(K(28, 5), char_width),
|
||||
"idle_alignment" : C(K(28, 1), char_width),
|
||||
}
|
||||
|
||||
class TX_Bootstrap(Module):
|
||||
def __init__(self):
|
||||
self.tx_testseq = Signal()
|
||||
|
||||
# # #
|
||||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
|
||||
self.source = stream.Endpoint(word_layout)
|
||||
|
||||
self.cnt = Signal(max=0xFFF)
|
||||
fsm.act("IDLE",
|
||||
If(self.tx_testseq,
|
||||
NextValue(self.cnt, self.cnt.reset),
|
||||
NextState("WRITE_TEST_PACKET_TYPE"),
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("WRITE_TEST_PACKET_TYPE",
|
||||
self.source.stb.eq(1),
|
||||
self.source.data.eq(Replicate(C(0x04, char_width), 4)),
|
||||
self.source.k.eq(Replicate(0, 4)),
|
||||
If(self.source.ack,NextState("WRITE_TEST_COUNTER"))
|
||||
)
|
||||
|
||||
# testword = Signal(word_dw)
|
||||
# self.comb += [
|
||||
# testword[:8].eq(self.cnt[:8]),
|
||||
# testword[8:16].eq(self.cnt[:8]+1),
|
||||
# testword[16:24].eq(self.cnt[:8]+2),
|
||||
# testword[24:].eq(self.cnt[:8]+3),
|
||||
# ]
|
||||
|
||||
fsm.act("WRITE_TEST_COUNTER",
|
||||
self.source.stb.eq(1),
|
||||
self.source.data[:8].eq(self.cnt[:8]),
|
||||
self.source.data[8:16].eq(self.cnt[:8]+1),
|
||||
self.source.data[16:24].eq(self.cnt[:8]+2),
|
||||
self.source.data[24:].eq(self.cnt[:8]+3),
|
||||
self.source.k.eq(Cat(0, 0, 0, 0)),
|
||||
If(self.source.ack,
|
||||
If(self.cnt == 0x0FF-3,
|
||||
self.source.eop.eq(1),
|
||||
NextState("IDLE")
|
||||
).Else(
|
||||
NextValue(self.cnt, self.cnt + 4),
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
class Idle_Word_Inserter(Module):
|
||||
def __init__(self):
|
||||
# Section 9.2.5 (CXP-001-2021)
|
||||
# Send K28.5, K28.1, K28.1, D21.5 as idle word
|
||||
self.submodules.fsm = fsm = FSM(reset_state="WRITE_IDLE")
|
||||
|
||||
self.sink = stream.Endpoint(word_layout)
|
||||
self.source = stream.Endpoint(word_layout)
|
||||
|
||||
cnt = Signal(max=0x10, reset=0xF)
|
||||
|
||||
fsm.act("WRITE_IDLE",
|
||||
self.source.stb.eq(1),
|
||||
self.source.data.eq(Cat(KCode["idle_comma"], KCode["idle_alignment"], KCode["idle_alignment"], C(0xB5, char_width))),
|
||||
self.source.k.eq(Cat(1, 1, 1, 0)),
|
||||
|
||||
self.sink.ack.eq(1),
|
||||
If(self.sink.stb,
|
||||
self.sink.ack.eq(0),
|
||||
If(self.source.ack,
|
||||
NextValue(cnt, cnt.reset),
|
||||
NextState("COPY"),
|
||||
)
|
||||
),
|
||||
)
|
||||
|
||||
fsm.act("COPY",
|
||||
self.sink.connect(self.source),
|
||||
# increment when upstream has data and got ack
|
||||
If(self.sink.stb & self.source.ack, NextValue(cnt, cnt - 1)),
|
||||
If((((~self.sink.stb) | (self.sink.eop) | (cnt == 0) ) & self.source.ack), NextState("WRITE_IDLE"))
|
||||
)
|
||||
|
||||
class Pipeline(Module):
|
||||
def __init__(self):
|
||||
self.submodules.bootstrap = boostrap = TX_Bootstrap()
|
||||
self.submodules.wrapper = wrapper = Packet_Wrapper()
|
||||
# self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
|
||||
self.submodules.idle_inserter = idle_inserter = Idle_Word_Inserter()
|
||||
|
||||
# # #
|
||||
|
||||
pipeline = [boostrap, wrapper, idle_inserter]
|
||||
for s, d in zip(pipeline, pipeline[1:]):
|
||||
self.comb += s.source.connect(d.sink)
|
||||
# self.sink = pipeline[0].sink
|
||||
self.source = pipeline[-1].source
|
||||
|
||||
# no backpressure
|
||||
# self.comb += self.source.ack.eq(1)
|
||||
|
||||
dut = Pipeline()
|
||||
|
||||
def check_case():
|
||||
source = dut.source
|
||||
# sink = dut.sink
|
||||
# for i in range(1, 30):
|
||||
# yield sink.data.eq(i)
|
||||
# yield sink.stb.eq(1)
|
||||
# yield
|
||||
yield dut.bootstrap.tx_testseq.eq(1)
|
||||
yield
|
||||
yield dut.bootstrap.tx_testseq.eq(0)
|
||||
for i in range(10):
|
||||
yield
|
||||
for _ in range(100):
|
||||
yield source.ack.eq(1)
|
||||
yield
|
||||
|
||||
|
||||
def testbench():
|
||||
yield from check_case()
|
||||
|
||||
|
||||
run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")
|
||||
12
src/gateware/cxp_rtio.py
Normal file
12
src/gateware/cxp_rtio.py
Normal file
@ -0,0 +1,12 @@
|
||||
# Clocking/Reset
|
||||
# Create rio and rio_phy domains based on sys
|
||||
# with reset controlled by CSR.
|
||||
#
|
||||
# The `rio` CD contains logic that is reset with `core.reset()`.
|
||||
# That's state that could unduly affect subsequent experiments,
|
||||
# i.e. input overflows caused by input gates left open, FIFO events far
|
||||
# in the future blocking the experiment, pending RTIO or
|
||||
# wishbone bus transactions, etc.
|
||||
# The `rio_phy` CD contains state that is maintained across
|
||||
# `core.reset()`, i.e. TTL output state, OE, DDS state.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user