forked from M-Labs/artiq-zynq
pipeline GW: add trig ack checker
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@ -13,6 +13,13 @@ downconn_layout = [("data", downconn_dw), ("k", downconn_dw//8)]
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def K(x, y):
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return ((y << 5) | x)
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def bytes2word(arr):
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assert len(arr) == 4
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sum = 0
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for i, val in enumerate(arr):
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sum += (val & 0xFF) << i*8
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return sum
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class Code_Source(Module):
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def __init__(self, layout, counts=4):
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@ -334,7 +341,7 @@ class TX_Test_Packet(Module, AutoCSR):
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self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(upconn_layout)
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self.comb += [
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pak_type_inserter.data.eq(0x04),
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pak_type_inserter.k.eq(0x04),
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pak_type_inserter.k.eq(0),
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testdata_src.connect(pak_type_inserter.sink),
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pak_type_inserter.source.connect(pak_wrp.sink),
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@ -366,3 +373,63 @@ class RX_Debug_Buffer(Module,AutoCSR):
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self.kout_pak.status.eq(buf_out.source.k),
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self.dout_valid.status.eq(buf_out.source.stb),
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]
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class Receiver_Path(Module, AutoCSR):
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def __init__(self):
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self.trig_ack = Signal()
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self.trig_clr = Signal()
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# TODO:
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self.packet_type = Signal(8)
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class CXP_Data_Packet_Decode(Module):
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def __init__(self):
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self.sink = stream.Endpoint(downconn_layout)
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# This is where data stream comes out
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self.source = stream.Endpoint(downconn_layout)
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# # #
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self.comb += self.sink.connect(self.source)
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class CXP_Trig_Ack_Checker(Module, AutoCSR):
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def __init__(self):
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self.sink = stream.Endpoint(downconn_layout)
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self.source = stream.Endpoint(downconn_layout)
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self.ack = Signal()
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# # #
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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self.sink.ack.eq(0),
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NextState("COPY"),
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)
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)
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fsm.act("COPY",
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If((self.sink.stb & (self.sink.data == bytes2word([K(28, 6)]*4)) & (self.sink.k == 0b1111)),
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# discard K28,6
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self.sink.ack.eq(1),
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NextState("CHECK_ACK")
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).Else(
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self.sink.connect(self.source),
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)
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)
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fsm.act("CHECK_ACK",
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If(self.sink.stb,
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NextState("IDLE"),
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# discard the word after K28,6
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self.sink.ack.eq(1),
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If(self.sink.data == bytes2word([0x01]*4),
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self.ack.eq(1),
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)
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)
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)
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