diff --git a/src/gateware/cxp_frame_pipeline.py b/src/gateware/cxp_frame_pipeline.py
index 4d9d1be..4a62aa6 100644
--- a/src/gateware/cxp_frame_pipeline.py
+++ b/src/gateware/cxp_frame_pipeline.py
@@ -2,6 +2,7 @@ from migen import *
 from misoc.interconnect.csr import *
 from misoc.interconnect.stream import Endpoint, SyncFIFO
 from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
+from misoc.cores.coaxpress.common import switch_endianness
 
 from misoc.cores.coaxpress.common import (
     char_width,
@@ -22,11 +23,6 @@ pixel4x_layout = [
     ("valid", 4), 
 ]
 
-def switch_endianness(s):
-    assert len(s) % 8 == 0
-    char = [s[i*8:(i+1)*8] for i in range(len(s)//8)]
-    return Cat(char[::-1])
-
 class End_Of_Line_Inserter(Module):
     """
     Insert eop to indicate end of line