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cxp upconn: add reset & tx_busy

This commit is contained in:
morgan 2024-08-30 18:07:00 +08:00
parent 6d00f52638
commit c06d9f8485
1 changed files with 18 additions and 6 deletions
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24
src/gateware/cxp_upconn.py
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@ -15,6 +15,7 @@ IDLE_CHARS = Array([
[0xB5, 0], #D21.5 [0xB5, 0], #D21.5
]) ])
@ResetInserter()
class UpConn_ClockGen(Module): class UpConn_ClockGen(Module):
def __init__(self, sys_clk_freq): def __init__(self, sys_clk_freq):
self.clk = Signal() self.clk = Signal()
@ -55,6 +56,8 @@ class UpConn_ClockGen(Module):
] ]
@ResetInserter()
@CEInserter()
class SERDES_10bits(Module): class SERDES_10bits(Module):
def __init__(self, pad): def __init__(self, pad):
self.oe = Signal() self.oe = Signal()
@ -89,6 +92,8 @@ class SERDES_10bits(Module):
) )
] ]
@ResetInserter()
@CEInserter()
class Packets_Scheduler(Module): class Packets_Scheduler(Module):
def __init__(self, tx_fifos): def __init__(self, tx_fifos):
self.tx_enable = Signal() self.tx_enable = Signal()
@ -182,14 +187,13 @@ class TxFIFOs(Module):
self.sink = [] self.sink = []
self.source_stb = Signal(nfifos)
self.source_ack = Array(Signal() for _ in range(nfifos)) self.source_ack = Array(Signal() for _ in range(nfifos))
self.source_data = Array(Signal(8) for _ in range(nfifos)) self.source_data = Array(Signal(8) for _ in range(nfifos))
self.source_k = Array(Signal() for _ in range(nfifos)) self.source_k = Array(Signal() for _ in range(nfifos))
# # # # # #
data_available = Signal(nfifos)
for i in range(nfifos): for i in range(nfifos):
fifo = stream.SyncFIFO(cxp_phy_layout, fifo_depth) fifo = stream.SyncFIFO(cxp_phy_layout, fifo_depth)
setattr(self.submodules, "tx_fifo" + str(i), fifo) setattr(self.submodules, "tx_fifo" + str(i), fifo)
@ -206,34 +210,42 @@ class TxFIFOs(Module):
fifo.source.ack.eq(0), fifo.source.ack.eq(0),
), ),
data_available[i].eq(fifo.source.stb), self.source_stb[i].eq(fifo.source.stb),
self.source_data[i].eq(fifo.source.data), self.source_data[i].eq(fifo.source.data),
self.source_k[i].eq(fifo.source.k), self.source_k[i].eq(fifo.source.k),
] ]
# FIFOs transmission priority # FIFOs transmission priority
self.submodules.pe = PriorityEncoder(nfifos) self.submodules.pe = PriorityEncoder(nfifos)
self.comb += self.pe.i.eq(data_available) self.comb += self.pe.i.eq(self.source_stb)
class CXP_UpConn(Module): class CXP_UpConn(Module):
def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout, fifo_depth, nfifos=3): def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout, fifo_depth, nfifos=3):
self.bitrate2x_enable = Signal() self.bitrate2x_enable = Signal()
self.clk_reset = Signal()
self.tx_enable = Signal() self.tx_enable = Signal()
self.tx_busy = Signal()
# # # # # #
self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq) self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
self.submodules.tx_fifos = tx_fifos = TxFIFOs(cxp_phy_layout, nfifos, fifo_depth) self.submodules.tx_fifos = tx_fifos = TxFIFOs(cxp_phy_layout, nfifos, fifo_depth)
self.submodules.scheduler = scheduler = CEInserter()(Packets_Scheduler(tx_fifos)) self.submodules.scheduler = scheduler = Packets_Scheduler(tx_fifos)
self.submodules.serdes = serdes = CEInserter()(SERDES_10bits(pad)) self.submodules.serdes = serdes = SERDES_10bits(pad)
self.comb += [ self.comb += [
self.tx_busy.eq(tx_fifos.source_stb != 0),
cg.reset.eq(self.clk_reset),
cg.freq2x_enable.eq(self.bitrate2x_enable), cg.freq2x_enable.eq(self.bitrate2x_enable),
scheduler.reset.eq(self.clk_reset),
scheduler.ce.eq(cg.clk), scheduler.ce.eq(cg.clk),
scheduler.tx_enable.eq(self.tx_enable), scheduler.tx_enable.eq(self.tx_enable),
serdes.reset.eq(self.clk_reset),
serdes.ce.eq(cg.clk_10x), serdes.ce.eq(cg.clk_10x),
serdes.d.eq(scheduler.encoder.output), serdes.d.eq(scheduler.encoder.output),
serdes.oe.eq(scheduler.oe), serdes.oe.eq(scheduler.oe),