forked from M-Labs/artiq-zynq
zc706: add upconn pads
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@ -690,7 +690,8 @@ class CXP_FMC():
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self.submodules.cxp = cxp.CXP(
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refclk=self.cdr_clk,
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pads=gtx_pads,
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downconn_pads=gtx_pads,
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upconn_pads=platform.request("CXP_LS", 0),
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sys_clk_freq=clk_freq,
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debug_sma=platform.request("user_sma_clock_33"),
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pmod_pads = pmod_pads
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