forked from M-Labs/artiq-zynq
cxp upconn: rename high speed upconn to bitrate2x
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d36afd6f7b
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bbf9e37867
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@ -11,7 +11,7 @@ class CXP_UpConn(Module, AutoCSR):
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self.clock_domains.cd_cxp_upconn = ClockDomain()
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self.clock_domains.cd_cxp_upconn = ClockDomain()
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self.clk_reset = CSRStorage(reset=1)
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self.clk_reset = CSRStorage(reset=1)
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self.high_speed_upconn = CSRStorage()
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self.bitrate2x_enable = CSRStorage()
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# # #
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# # #
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@ -42,7 +42,7 @@ class CXP_UpConn(Module, AutoCSR):
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Instance("BUFGMUX",
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Instance("BUFGMUX",
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i_I0=pll_cxpclk,
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i_I0=pll_cxpclk,
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i_I1=pll_cxpclk2x,
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i_I1=pll_cxpclk2x,
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i_S=self.high_speed_upconn.storage,
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i_S=self.bitrate2x_enable.storage,
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o_O=self.cd_cxp_upconn.clk
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o_O=self.cd_cxp_upconn.clk
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),
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),
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AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset.storage)
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AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset.storage)
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