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pipeline GW: move buffer depth&count into fn args

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morgan 2025-01-23 11:39:51 +08:00
parent d6530e9b78
commit b9fe94d2d4
1 changed files with 5 additions and 9 deletions
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14
src/gateware/cxp_pipeline.py
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@ -20,9 +20,6 @@ word_layout_dchar = [
("dchar_k", char_width//8), ("dchar_k", char_width//8),
] ]
buffer_count = 4
buffer_depth = 512
def K(x, y): def K(x, y):
return ((y << 5) | x) return ((y << 5) | x)
@ -202,7 +199,7 @@ class Trigger_ACK_Inserter(Module):
@FullMemoryWE() @FullMemoryWE()
class Control_Packet_Writer(Module): class Control_Packet_Writer(Module):
def __init__(self): def __init__(self, buffer_depth):
self.word_len = Signal(log2_int(buffer_depth)) self.word_len = Signal(log2_int(buffer_depth))
self.stb = Signal() self.stb = Signal()
self.stb_testseq = Signal() self.stb_testseq = Signal()
@ -366,7 +363,7 @@ class Duplicated_Char_Decoder(Module):
@FullMemoryWE() @FullMemoryWE()
class Control_Packet_Reader(Module): class Control_Packet_Reader(Module):
def __init__(self): def __init__(self, buffer_depth, nslot):
self.packet_type = Signal(8) self.packet_type = Signal(8)
self.decode_err = Signal() self.decode_err = Signal()
@ -492,8 +489,8 @@ class Control_Packet_Reader(Module):
) )
] ]
# A circular buffer for firmware to read packet from # N buffers for firmware to read packet from
self.specials.mem = mem = Memory(word_width, buffer_count*buffer_depth) self.specials.mem = mem = Memory(word_width, nslot*buffer_depth)
self.specials.mem_port = mem_port = mem.get_port(write_capable=True) self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
# buffered mem_port to improve timing # buffered mem_port to improve timing
@ -506,7 +503,7 @@ class Control_Packet_Reader(Module):
mem_port.adr.eq(buf_mem_adr) mem_port.adr.eq(buf_mem_adr)
] ]
write_ptr = Signal(log2_int(buffer_count)) write_ptr = Signal(log2_int(nslot))
self.write_ptr_sys = Signal.like(write_ptr) self.write_ptr_sys = Signal.like(write_ptr)
self.specials += MultiReg(write_ptr, self.write_ptr_sys), self.specials += MultiReg(write_ptr, self.write_ptr_sys),
@ -515,7 +512,6 @@ class Control_Packet_Reader(Module):
buf_mem_adr[addr_nbits:].eq(write_ptr), buf_mem_adr[addr_nbits:].eq(write_ptr),
] ]
# For control ack, event packet
fsm.act("LOAD_BUFFER", fsm.act("LOAD_BUFFER",
buf_mem_we.eq(0), buf_mem_we.eq(0),
self.sink.ack.eq(1), self.sink.ack.eq(1),