From b9fe94d2d484f34a8a1f1b7ec5ae12f927791713 Mon Sep 17 00:00:00 2001 From: morgan Date: Thu, 23 Jan 2025 11:39:51 +0800 Subject: [PATCH] pipeline GW: move buffer depth&count into fn args --- src/gateware/cxp_pipeline.py | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/src/gateware/cxp_pipeline.py b/src/gateware/cxp_pipeline.py index caf1556..10a8a95 100644 --- a/src/gateware/cxp_pipeline.py +++ b/src/gateware/cxp_pipeline.py @@ -20,9 +20,6 @@ word_layout_dchar = [ ("dchar_k", char_width//8), ] -buffer_count = 4 -buffer_depth = 512 - def K(x, y): return ((y << 5) | x) @@ -202,7 +199,7 @@ class Trigger_ACK_Inserter(Module): @FullMemoryWE() class Control_Packet_Writer(Module): - def __init__(self): + def __init__(self, buffer_depth): self.word_len = Signal(log2_int(buffer_depth)) self.stb = Signal() self.stb_testseq = Signal() @@ -366,7 +363,7 @@ class Duplicated_Char_Decoder(Module): @FullMemoryWE() class Control_Packet_Reader(Module): - def __init__(self): + def __init__(self, buffer_depth, nslot): self.packet_type = Signal(8) self.decode_err = Signal() @@ -492,8 +489,8 @@ class Control_Packet_Reader(Module): ) ] - # A circular buffer for firmware to read packet from - self.specials.mem = mem = Memory(word_width, buffer_count*buffer_depth) + # N buffers for firmware to read packet from + self.specials.mem = mem = Memory(word_width, nslot*buffer_depth) self.specials.mem_port = mem_port = mem.get_port(write_capable=True) # buffered mem_port to improve timing @@ -506,7 +503,7 @@ class Control_Packet_Reader(Module): mem_port.adr.eq(buf_mem_adr) ] - write_ptr = Signal(log2_int(buffer_count)) + write_ptr = Signal(log2_int(nslot)) self.write_ptr_sys = Signal.like(write_ptr) self.specials += MultiReg(write_ptr, self.write_ptr_sys), @@ -515,7 +512,6 @@ class Control_Packet_Reader(Module): buf_mem_adr[addr_nbits:].eq(write_ptr), ] - # For control ack, event packet fsm.act("LOAD_BUFFER", buf_mem_we.eq(0), self.sink.ack.eq(1),