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cxp upconn: send IDLE every 10000 words & cleanup

This commit is contained in:
morgan 2024-08-26 16:44:45 +08:00
parent 2aa194390f
commit b8aea61fd8
1 changed files with 49 additions and 42 deletions
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91
src/gateware/cxp_upconn.py
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@ -51,33 +51,33 @@ class CXP_UpConn(Module, AutoCSR):
] ]
self.submodules.fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE")) self.submodules.fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE"))
self.submodules.tx_fifos = TxFIFOs(self.nfifos, fifo_depth) self.submodules.tx_fifos = tx_fifos = TxFIFOs(self.nfifos, fifo_depth)
self.submodules.tx_idle = TxIdle() self.submodules.tx_idle = tx_idle = TxIdle()
o = Signal() o = Signal()
tx_en = Signal() tx_en = Signal()
tx_bitcount = Signal(max=10) tx_bitcount = Signal(max=10)
tx_charcount = Signal(max=4) tx_charcount = Signal(max=4)
tx_wordcount = Signal(max=10000)
tx_reg = Signal(10) tx_reg = Signal(10)
priorities = Signal(max=self.nfifos) priorities = Signal(max=self.nfifos)
idling = Signal() idling = Signal()
encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True)) self.submodules.encoder = encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
self.submodules += encoder
# startup sequence # startup sequence
self.fsm.act("WAIT_TX_ENABLE", self.fsm.act("WAIT_TX_ENABLE",
If(self.tx_enable.storage, If(self.tx_enable.storage,
NextValue(self.tx_idle.word_idx, 0), NextValue(tx_idle.word_idx, 0),
NextState("ENCODE_CHAR") NextState("ENCODE_CHAR")
) )
) )
self.fsm.act("ENCODE_CHAR", self.fsm.act("ENCODE_CHAR",
NextValue(self.tx_idle.source_ack, 1), NextValue(tx_idle.source_ack, 1),
NextValue(encoder.d, self.tx_idle.source_data), NextValue(encoder.d, tx_idle.source_data),
NextValue(encoder.k, self.tx_idle.source_k), NextValue(encoder.k, tx_idle.source_k),
NextState("LOAD_CHAR"), NextState("LOAD_CHAR"),
) )
@ -115,38 +115,45 @@ class CXP_UpConn(Module, AutoCSR):
If(tx_bitcount == 9, If(tx_bitcount == 9,
# Section 9.2.4 (CXP-001-2021) # Section 9.2.4 (CXP-001-2021)
# trigger packets should be inserted at char boundary # trigger packets should be inserted at char boundary
If((~self.tx_fifos.pe.n) & (self.tx_fifos.pe.o == 0), If((~tx_fifos.pe.n) & (tx_fifos.pe.o == 0),
# trigger packets are inserted at char boundary and don't contribute to word count # trigger packets are inserted at char boundary and don't contribute to word count
self.tx_fifos.source_ack[0].eq(1), tx_fifos.source_ack[0].eq(1),
encoder.d.eq(self.tx_fifos.source_data[0]), encoder.d.eq(tx_fifos.source_data[0]),
encoder.k.eq(self.tx_fifos.source_k[0]), encoder.k.eq(tx_fifos.source_k[0]),
).Else( ).Else(
If(tx_charcount == 3, If(tx_charcount == 3,
tx_charcount.eq(0), tx_charcount.eq(0),
# Section 9.2.4 (CXP-001-2021)
# other priorities packets are inserted at word boundary # other priorities packets are inserted at word boundary
If(~self.tx_fifos.pe.n, If((~tx_fifos.pe.n) & (tx_wordcount != 9999),
idling.eq(0), idling.eq(0),
priorities.eq(self.tx_fifos.pe.o), priorities.eq(tx_fifos.pe.o),
self.tx_fifos.source_ack[self.tx_fifos.pe.o].eq(1), tx_wordcount.eq(tx_wordcount + 1),
encoder.d.eq(self.tx_fifos.source_data[self.tx_fifos.pe.o]),
encoder.k.eq(self.tx_fifos.source_k[self.tx_fifos.pe.o]), tx_fifos.source_ack[tx_fifos.pe.o].eq(1),
encoder.d.eq(tx_fifos.source_data[tx_fifos.pe.o]),
encoder.k.eq(tx_fifos.source_k[tx_fifos.pe.o]),
).Else( ).Else(
# Section 9.2.5.1 (CXP-001-2021)
# IDLE word shall be transmitted at least once every 10,000 words, but should not be inserted into trigger packet
idling.eq(1), idling.eq(1),
self.tx_idle.source_ack.eq(1), tx_wordcount.eq(0),
encoder.d.eq(self.tx_idle.source_data),
encoder.k.eq(self.tx_idle.source_k), tx_idle.source_ack.eq(1),
encoder.d.eq(tx_idle.source_data),
encoder.k.eq(tx_idle.source_k),
) )
).Else( ).Else(
tx_charcount.eq(tx_charcount + 1), tx_charcount.eq(tx_charcount + 1),
If(~idling, If(~idling,
self.tx_fifos.source_ack[priorities].eq(1), tx_fifos.source_ack[priorities].eq(1),
encoder.d.eq(self.tx_fifos.source_data[priorities]), encoder.d.eq(tx_fifos.source_data[priorities]),
encoder.k.eq(self.tx_fifos.source_k[priorities]), encoder.k.eq(tx_fifos.source_k[priorities]),
).Else( ).Else(
self.tx_idle.source_ack.eq(1), tx_idle.source_ack.eq(1),
encoder.d.eq(self.tx_idle.source_data), encoder.d.eq(tx_idle.source_data),
encoder.k.eq(self.tx_idle.source_k), encoder.k.eq(tx_idle.source_k),
) )
), ),
) )
@ -169,10 +176,10 @@ class CXP_UpConn(Module, AutoCSR):
p0 = Signal() p0 = Signal()
p3 = Signal() p3 = Signal()
self.comb += [ self.comb += [
prioity_0.eq((~self.tx_fifos.pe.n) & (self.tx_fifos.pe.o == 0)), prioity_0.eq((~tx_fifos.pe.n) & (tx_fifos.pe.o == 0)),
word_bound.eq(tx_charcount == 3), word_bound.eq(tx_charcount == 3),
p0.eq(self.tx_idle.word_idx == 0), p0.eq(tx_idle.word_idx == 0),
p3.eq(self.tx_idle.word_idx == 3), p3.eq(tx_idle.word_idx == 3),
] ]
self.specials += [ self.specials += [
# # debug sma # # debug sma
@ -182,13 +189,13 @@ class CXP_UpConn(Module, AutoCSR):
# # pmod 0-7 pin # # pmod 0-7 pin
Instance("OBUF", i_I=o, o_O=pmod[0]), Instance("OBUF", i_I=o, o_O=pmod[0]),
Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pmod[1]), Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pmod[1]),
Instance("OBUF", i_I=~self.tx_fifos.pe.n, o_O=pmod[2]), Instance("OBUF", i_I=~tx_fifos.pe.n, o_O=pmod[2]),
Instance("OBUF", i_I=prioity_0, o_O=pmod[3]), Instance("OBUF", i_I=prioity_0, o_O=pmod[3]),
Instance("OBUF", i_I=word_bound, o_O=pmod[4]), Instance("OBUF", i_I=word_bound, o_O=pmod[4]),
Instance("OBUF", i_I=idling, o_O=pmod[5]), Instance("OBUF", i_I=idling, o_O=pmod[5]),
# Instance("OBUF", i_I=self.tx_fifos.source_ack[0], o_O=pmod[6]), # Instance("OBUF", i_I=tx_fifos.source_ack[0], o_O=pmod[6]),
# Instance("OBUF", i_I=self.tx_fifos.source_ack[2], o_O=pmod[6]), # Instance("OBUF", i_I=tx_fifos.source_ack[2], o_O=pmod[6]),
# Instance("OBUF", i_I=self.tx_fifos.source_ack[1], o_O=pmod[7]), # Instance("OBUF", i_I=tx_fifos.source_ack[1], o_O=pmod[7]),
Instance("OBUF", i_I=p0, o_O=pmod[6]), Instance("OBUF", i_I=p0, o_O=pmod[6]),
Instance("OBUF", i_I=p3, o_O=pmod[7]), Instance("OBUF", i_I=p3, o_O=pmod[7]),
] ]
@ -197,17 +204,17 @@ class CXP_UpConn(Module, AutoCSR):
self.symbol2 = CSR(9) self.symbol2 = CSR(9)
self.sync += [ self.sync += [
self.tx_fifos.sink_stb[0].eq(self.symbol0.re), tx_fifos.sink_stb[0].eq(self.symbol0.re),
self.tx_fifos.sink_data[0].eq(self.symbol0.r[:8]), tx_fifos.sink_data[0].eq(self.symbol0.r[:8]),
self.tx_fifos.sink_k[0].eq(self.symbol0.r[8]), tx_fifos.sink_k[0].eq(self.symbol0.r[8]),
self.tx_fifos.sink_stb[1].eq(self.symbol1.re), tx_fifos.sink_stb[1].eq(self.symbol1.re),
self.tx_fifos.sink_data[1].eq(self.symbol1.r[:8]), tx_fifos.sink_data[1].eq(self.symbol1.r[:8]),
self.tx_fifos.sink_k[1].eq(self.symbol1.r[8]), tx_fifos.sink_k[1].eq(self.symbol1.r[8]),
self.tx_fifos.sink_stb[2].eq(self.symbol2.re), tx_fifos.sink_stb[2].eq(self.symbol2.re),
self.tx_fifos.sink_data[2].eq(self.symbol2.r[:8]), tx_fifos.sink_data[2].eq(self.symbol2.r[:8]),
self.tx_fifos.sink_k[2].eq(self.symbol2.r[8]), tx_fifos.sink_k[2].eq(self.symbol2.r[8]),
] ]
class TxFIFOs(Module): class TxFIFOs(Module):