forked from M-Labs/artiq-zynq
cxp GW: wrap gtxs into downconn interface
This commit is contained in:
parent
fe57067f70
commit
b725594a1d
|
@ -10,11 +10,20 @@ class CXP(Module, AutoCSR):
|
|||
def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
|
||||
self.submodules.upconn = UpConn_Interface(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
|
||||
|
||||
self.submodules.downconn = CXP_DownConn_PHY(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
|
||||
self.submodules.downconn = DownConn_Interface(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
|
||||
# TODO: support the option high speed upconn
|
||||
|
||||
# TODO: add link layer
|
||||
|
||||
class DownConn_Interface(Module, AutoCSR):
|
||||
def __init__(self, refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads):
|
||||
|
||||
# # #
|
||||
|
||||
self.submodules.phy = phy = CXP_DownConn_PHY(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
|
||||
self.gtxs = phy.gtxs
|
||||
|
||||
|
||||
|
||||
class UpConn_Interface(Module, AutoCSR):
|
||||
def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
|
||||
|
|
Loading…
Reference in New Issue