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CXP CLK alignment: clock domain naming refactor

This commit is contained in:
morgan 2024-06-13 16:56:36 +08:00
parent 9c69167f7f
commit b52589bd5f
1 changed files with 3 additions and 3 deletions
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6
src/gateware/coaxpress_clock_align.py
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@ -47,7 +47,7 @@ class CXP_BruteforceClockAligner(Module):
) )
] ]
checks_reset = PulseSynchronizer("sys", "cxp_rx") checks_reset = PulseSynchronizer("sys", "cxp_gtx_rx")
self.submodules += checks_reset self.submodules += checks_reset
comma_n = ~comma & 0b1111111111 comma_n = ~comma & 0b1111111111
@ -55,7 +55,7 @@ class CXP_BruteforceClockAligner(Module):
comma_seen = Signal() comma_seen = Signal()
comma_seen_rxclk.attr.add("no_retiming") comma_seen_rxclk.attr.add("no_retiming")
self.specials += MultiReg(comma_seen_rxclk, comma_seen) self.specials += MultiReg(comma_seen_rxclk, comma_seen)
self.sync.cxp_rx += \ self.sync.cxp_gtx_rx += \
If(checks_reset.o, If(checks_reset.o,
comma_seen_rxclk.eq(0) comma_seen_rxclk.eq(0)
).Elif((self.rxdata[:10] == comma) | (self.rxdata[:10] == comma_n), ).Elif((self.rxdata[:10] == comma) | (self.rxdata[:10] == comma_n),
@ -67,7 +67,7 @@ class CXP_BruteforceClockAligner(Module):
error_seen_rxclk.attr.add("no_retiming") error_seen_rxclk.attr.add("no_retiming")
self.specials += MultiReg(error_seen_rxclk, error_seen) self.specials += MultiReg(error_seen_rxclk, error_seen)
rx1cnt = Signal(max=11) rx1cnt = Signal(max=11)
self.sync.cxp_rx += [ self.sync.cxp_gtx_rx += [
rx1cnt.eq(reduce(add, [self.rxdata[i] for i in range(10)])), rx1cnt.eq(reduce(add, [self.rxdata[i] for i in range(10)])),
If(checks_reset.o, If(checks_reset.o,
error_seen_rxclk.eq(0) error_seen_rxclk.eq(0)