diff --git a/src/gateware/coaxpress_clock_align.py b/src/gateware/coaxpress_clock_align.py
index 728ddb2..73fb0eb 100644
--- a/src/gateware/coaxpress_clock_align.py
+++ b/src/gateware/coaxpress_clock_align.py
@@ -47,7 +47,7 @@ class CXP_BruteforceClockAligner(Module):
             )
         ]
 
-        checks_reset = PulseSynchronizer("sys", "cxp_rx")
+        checks_reset = PulseSynchronizer("sys", "cxp_gtx_rx")
         self.submodules += checks_reset
 
         comma_n = ~comma & 0b1111111111
@@ -55,7 +55,7 @@ class CXP_BruteforceClockAligner(Module):
         comma_seen = Signal()
         comma_seen_rxclk.attr.add("no_retiming")
         self.specials += MultiReg(comma_seen_rxclk, comma_seen)
-        self.sync.cxp_rx += \
+        self.sync.cxp_gtx_rx += \
             If(checks_reset.o,
                 comma_seen_rxclk.eq(0)
             ).Elif((self.rxdata[:10] == comma) | (self.rxdata[:10] == comma_n),
@@ -67,7 +67,7 @@ class CXP_BruteforceClockAligner(Module):
         error_seen_rxclk.attr.add("no_retiming")
         self.specials += MultiReg(error_seen_rxclk, error_seen)
         rx1cnt = Signal(max=11)
-        self.sync.cxp_rx += [
+        self.sync.cxp_gtx_rx += [
             rx1cnt.eq(reduce(add, [self.rxdata[i] for i in range(10)])),
             If(checks_reset.o,
                 error_seen_rxclk.eq(0)