forked from M-Labs/artiq-zynq
proto FW: add memory write test
proto FW: fix compilation error
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@ -1,10 +1,12 @@
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use core::slice;
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use core_io::{Error as IoError, Write};
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use crc::crc32;
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use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
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use io::Cursor;
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use libboard_zynq::{println, timer::GlobalTimer};
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use crate::pl::csr;
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use crate::{mem::mem::CXP_MEM, pl::csr};
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const MAX_PACKET: usize = 128;
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const DATA_MAXSIZE: usize = /*max size*/MAX_PACKET - /*Tag*/4 - /*Op code & length*/4 - /*addr*/4 - /*CRC*/4 ;
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@ -243,3 +245,37 @@ pub fn downconn_send_test_packet() {
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while csr::cxp::downconn_testseq_busy_read() == 1 {}
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}
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}
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pub fn ram_writer_send(packet: &Packet) -> Result<(), Error> {
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unsafe {
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// TODO: put this in mem group
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while csr::cxp::transmitter_cxp_tx_read() == 1 {}
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let ptr = CXP_MEM[0].base as *mut u32;
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let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, 0x200 as usize));
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packet.write_to(&mut writer)?;
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csr::cxp::transmitter_cxp_tx_word_len_write(writer.position() as u8 / 4);
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csr::cxp::transmitter_cxp_tx_write(1);
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while csr::cxp::transmitter_cxp_tx_read() == 1 {}
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// read the fifo
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const LEN: usize = 10;
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let mut pak_arr: [u32; LEN] = [0; LEN];
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let mut k_arr: [u8; LEN] = [0; LEN];
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let mut i: usize = 0;
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while csr::cxp::transmitter_debug_out_dout_valid_read() == 1 {
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pak_arr[i] = csr::cxp::transmitter_debug_out_dout_pak_read();
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k_arr[i] = csr::cxp::transmitter_debug_out_kout_pak_read();
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// println!("received {:#04X}", pak_arr[i]);
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csr::cxp::transmitter_debug_out_inc_write(1);
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i += 1;
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if i == LEN {
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break;
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}
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}
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print_packetu32(&pak_arr, &k_arr);
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}
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Ok(())
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}
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