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cxp upconn: add a debug fifo output b4 seders

This commit is contained in:
morgan 2024-09-02 12:24:59 +08:00
parent 30be11aef2
commit b1fb90d456
1 changed files with 112 additions and 24 deletions
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110
src/gateware/cxp_upconn.py
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@ -95,7 +95,7 @@ class SERDES_10bits(Module):
@ResetInserter()
@CEInserter()
class Packets_Scheduler(Module):
def __init__(self, tx_fifos):
def __init__(self, tx_fifos, buf_out):
self.tx_enable = Signal()
self.oe = Signal()
@ -144,6 +144,13 @@ class Packets_Scheduler(Module):
tx_fifos.source_ack[0].eq(1),
encoder.d.eq(tx_fifos.source_data[0]),
encoder.k.eq(tx_fifos.source_k[0]),
# DEBUG:
If(buf_out.sink_ack,
buf_out.sink_stb.eq(1),
buf_out.sink_data.eq(tx_fifos.source_data[0]),
buf_out.sink_k.eq(tx_fifos.source_k[0]),
)
).Else(
If(tx_charcount == 3,
tx_charcount.eq(0),
@ -158,6 +165,13 @@ class Packets_Scheduler(Module):
tx_fifos.source_ack[tx_fifos.pe.o].eq(1),
encoder.d.eq(tx_fifos.source_data[tx_fifos.pe.o]),
encoder.k.eq(tx_fifos.source_k[tx_fifos.pe.o]),
# DEBUG:
If(buf_out.sink_ack,
buf_out.sink_stb.eq(1),
buf_out.sink_data.eq(tx_fifos.source_data[tx_fifos.pe.o]),
buf_out.sink_k.eq(tx_fifos.source_k[tx_fifos.pe.o]),
)
).Else(
# Section 9.2.5.1 (CXP-001-2021)
# IDLE word shall be transmitted at least once every 10,000 words, but should not be inserted into trigger packet
@ -166,6 +180,13 @@ class Packets_Scheduler(Module):
encoder.d.eq(IDLE_CHARS[0][0]),
encoder.k.eq(IDLE_CHARS[0][1]),
# DEBUG:
# If(buf_out.sink.ack,
# buf_out.sink.stb.eq(1),
# buf_out.sink.data.eq(IDLE_CHARS[0][0]),
# buf_out.sink.k.eq(IDLE_CHARS[0][1]),
# )
)
).Else(
tx_charcount.eq(tx_charcount + 1),
@ -173,9 +194,23 @@ class Packets_Scheduler(Module):
tx_fifos.source_ack[priorities].eq(1),
encoder.d.eq(tx_fifos.source_data[priorities]),
encoder.k.eq(tx_fifos.source_k[priorities]),
# DEBUG:
If(buf_out.sink_ack,
buf_out.sink_stb.eq(1),
buf_out.sink_data.eq(tx_fifos.source_data[priorities]),
buf_out.sink_k.eq(tx_fifos.source_k[priorities]),
)
).Else(
encoder.d.eq(IDLE_CHARS[tx_charcount + 1][0]),
encoder.k.eq(IDLE_CHARS[tx_charcount + 1][1]),
# DEBUG:
# If(buf_out.sink.ack,
# buf_out.sink.stb.eq(1),
# buf_out.sink.data.eq(IDLE_CHARS[tx_charcount + 1][0]),
# buf_out.sink.k.eq(IDLE_CHARS[tx_charcount + 1][1]),
# )
)
),
),
@ -183,7 +218,7 @@ class Packets_Scheduler(Module):
]
class TxFIFOs(Module):
def __init__(self, cxp_phy_layout, nfifos, fifo_depth):
def __init__(self, layout, nfifos, fifo_depth):
self.sink = []
@ -195,7 +230,7 @@ class TxFIFOs(Module):
# # #
for i in range(nfifos):
fifo = stream.SyncFIFO(cxp_phy_layout, fifo_depth)
fifo = stream.SyncFIFO(layout, fifo_depth)
setattr(self.submodules, "tx_fifo" + str(i), fifo)
self.sink += [fifo.sink]
@ -219,8 +254,50 @@ class TxFIFOs(Module):
self.submodules.pe = PriorityEncoder(nfifos)
self.comb += self.pe.i.eq(self.source_stb)
class CXP_UpConn_PHY(Module):
def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout, fifo_depth, nfifos=3):
class Debug_buffer(Module,AutoCSR):
def __init__(self, layout):
self.sink_stb = Signal()
self.sink_ack = Signal()
self.sink_data = Signal(8)
self.sink_k = Signal()
# # #
self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, 128)
self.sync += [
If(self.sink_stb,
# reset ack after asserted
# since upconn clk run much slower, the ack will be high for longer than expected which will result in data loss
self.sink_stb.eq(0),
buf_out.sink.stb.eq(1),
).Else(
buf_out.sink.stb.eq(0),
),
self.sink_ack.eq(buf_out.sink.ack),
buf_out.sink.data.eq(self.sink_data),
buf_out.sink.k.eq(self.sink_k),
]
self.inc = CSR()
self.dout_pak = CSRStatus(8)
self.kout_pak = CSRStatus()
self.dout_valid = CSRStatus()
self.sync += [
# output
buf_out.source.ack.eq(self.inc.re),
self.dout_pak.status.eq(buf_out.source.data),
self.kout_pak.status.eq(buf_out.source.k),
self.dout_valid.status.eq(buf_out.source.stb),
]
class CXP_UpConn_PHY(Module, AutoCSR):
def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, layout, fifo_depth, nfifos=3):
self.bitrate2x_enable = Signal()
self.clk_reset = Signal()
@ -230,9 +307,12 @@ class CXP_UpConn_PHY(Module):
# # #
self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
self.submodules.tx_fifos = tx_fifos = TxFIFOs(cxp_phy_layout, nfifos, fifo_depth)
self.submodules.tx_fifos = tx_fifos = TxFIFOs(layout, nfifos, fifo_depth)
self.submodules.scheduler = scheduler = Packets_Scheduler(tx_fifos)
# DEBUG:
self.submodules.debug_buf = debug_buf = Debug_buffer(layout)
self.submodules.scheduler = scheduler = Packets_Scheduler(tx_fifos, debug_buf)
self.submodules.serdes = serdes = SERDES_10bits(pad)
self.comb += [
@ -265,13 +345,21 @@ class CXP_UpConn_PHY(Module):
# because of clk delay
p0.eq(scheduler.tx_charcount == 2),
p3.eq(scheduler.tx_charcount == 1),
]
# self.specials += [
# # # debug sma
self.specials += [
# # debug sma
# Instance("OBUF", i_I=cg.clk, o_O=debug_sma.p_tx),
# Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx),
# # # pmod 0-7 pin
# pmod 0-7 pin
Instance("OBUF", i_I=debug_buf.buf_out.sink.stb, o_O=pmod_pads[4]),
Instance("OBUF", i_I=debug_buf.buf_out.sink.ack, o_O=pmod_pads[5]),
Instance("OBUF", i_I=debug_buf.buf_out.source.stb, o_O=pmod_pads[6]),
Instance("OBUF", i_I=debug_buf.buf_out.source.ack, o_O=pmod_pads[7]),
# # pmod 0-7 pin
# Instance("OBUF", i_I=serdes.o, o_O=pmod_pads[0]),
# Instance("OBUF", i_I=cg.clk_10x, o_O=pmod_pads[1]),
# Instance("OBUF", i_I=~tx_fifos.pe.n, o_O=pmod_pads[2]),
@ -283,5 +371,5 @@ class CXP_UpConn_PHY(Module):
# # Instance("OBUF", i_I=tx_fifos.source_ack[1], o_O=pmod[7]),
# Instance("OBUF", i_I=p0, o_O=pmod_pads[6]),
# Instance("OBUF", i_I=p3, o_O=pmod_pads[7]),
# ]
]