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cxp pipeline: refactor tx command

This commit is contained in:
morgan 2024-09-05 11:37:58 +08:00
parent f2d7a67da3
commit ac52109a06
1 changed files with 23 additions and 28 deletions
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51
src/gateware/cxp_pipeline.py
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@ -1,7 +1,7 @@
from migen import * from migen import *
from misoc.interconnect.csr import * from misoc.interconnect.csr import *
from misoc.interconnect import stream from misoc.interconnect import stream
from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCInserter from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCChecker
def K(x, y): def K(x, y):
return ((y << 5) | x) return ((y << 5) | x)
@ -179,9 +179,9 @@ class CXPCRC32(Module):
self.error.eq(self.engine.next != self.check) self.error.eq(self.engine.next != self.check)
] ]
class CXPCRC32Inserter(LiteEthMACCRCInserter): class CXPCRC32Checker(LiteEthMACCRCChecker):
def __init__(self, layout): def __init__(self, layout):
LiteEthMACCRCInserter.__init__(self, CXPCRC32, layout) LiteEthMACCRCChecker.__init__(self, CXPCRC32, layout)
class TX_Trigger(Module, AutoCSR): class TX_Trigger(Module, AutoCSR):
def __init__(self, layout): def __init__(self, layout):
@ -243,35 +243,30 @@ class Trigger_ACK(Module):
class TX_Command_Packet(Module, AutoCSR): class TX_Command_Packet(Module, AutoCSR):
def __init__(self, layout): def __init__(self, layout):
self.din_len = CSRStorage(6) self.len = CSRStorage(6)
self.din_data = CSR(8) self.data = CSR(8)
self.din_ready = CSRStatus() self.writeable = CSRStatus()
# # # # # #
# a buf is used to simulated a proper endpoint which hold source.stb high as long as data is available
# otherwise, CSR.re only hold when CSR is written to and it cannot act as a proper source
self.submodules.buf_in = buf_in = stream.SyncFIFO(layout, 2)
self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(layout) self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(layout)
self.source = pak_wrp.source
len = Signal(6, reset=1) len = Signal(6, reset=1)
self.sync += [ self.sync += [
self.din_ready.status.eq(buf_in.sink.ack), self.writeable.status.eq(pak_wrp.sink.ack),
buf_in.sink.stb.eq(0), If(pak_wrp.sink.ack,pak_wrp.sink.stb.eq(0)),
If(self.din_data.re, If(self.data.re,
If(len == self.din_len.storage, pak_wrp.sink.stb.eq(1),
len.eq(len.reset), pak_wrp.sink.data.eq(self.data.r),
buf_in.sink.eop.eq(1),
).Else(
len.eq(len + 1),
buf_in.sink.eop.eq(0),
),
buf_in.sink.stb.eq(1),
buf_in.sink.data.eq(self.din_data.r),
buf_in.sink.k.eq(0),
),
]
self.comb += buf_in.source.connect(pak_wrp.sink), pak_wrp.sink.k.eq(0),
self.source = pak_wrp.source If(len == self.len.storage,
pak_wrp.sink.eop.eq(1),
len.eq(len.reset),
).Else(
pak_wrp.sink.eop.eq(0),
len.eq(len + 1),
),
)
]