From ac52109a06fcb78550470437d3eae8b8cc0cb505 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Thu, 5 Sep 2024 11:37:58 +0800
Subject: [PATCH] cxp pipeline: refactor tx command

---
 src/gateware/cxp_pipeline.py | 51 ++++++++++++++++--------------------
 1 file changed, 23 insertions(+), 28 deletions(-)

diff --git a/src/gateware/cxp_pipeline.py b/src/gateware/cxp_pipeline.py
index a9d6213..80b9148 100644
--- a/src/gateware/cxp_pipeline.py
+++ b/src/gateware/cxp_pipeline.py
@@ -1,7 +1,7 @@
 from migen import *
 from misoc.interconnect.csr import *
 from misoc.interconnect import stream
-from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCInserter 
+from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCChecker
 
 def K(x, y):
     return ((y << 5) | x)
@@ -179,9 +179,9 @@ class CXPCRC32(Module):
             self.error.eq(self.engine.next != self.check)
         ]
 
-class CXPCRC32Inserter(LiteEthMACCRCInserter):
+class CXPCRC32Checker(LiteEthMACCRCChecker):
     def __init__(self, layout):
-        LiteEthMACCRCInserter.__init__(self, CXPCRC32, layout)
+        LiteEthMACCRCChecker.__init__(self, CXPCRC32, layout)
 
 class TX_Trigger(Module, AutoCSR):
     def __init__(self, layout):
@@ -243,35 +243,30 @@ class Trigger_ACK(Module):
 
 class TX_Command_Packet(Module, AutoCSR):
     def __init__(self, layout):
-        self.din_len = CSRStorage(6)
-        self.din_data = CSR(8)
-        self.din_ready = CSRStatus()
+        self.len = CSRStorage(6)
+        self.data = CSR(8)
+        self.writeable = CSRStatus()
 
         # # #
 
-        # a buf is used to simulated a proper endpoint which hold source.stb high as long as data is available
-        # otherwise, CSR.re only hold when CSR is written to and it cannot act as a proper source
-        self.submodules.buf_in = buf_in = stream.SyncFIFO(layout, 2)
-
         self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(layout)
-        
+        self.source = pak_wrp.source
+
         len = Signal(6, reset=1)
         self.sync += [
-            self.din_ready.status.eq(buf_in.sink.ack),
-            buf_in.sink.stb.eq(0),
-            If(self.din_data.re,
-                If(len == self.din_len.storage,
-                    len.eq(len.reset),
-                    buf_in.sink.eop.eq(1),
-                ).Else(
-                    len.eq(len + 1),
-                    buf_in.sink.eop.eq(0),
-                ),
-                buf_in.sink.stb.eq(1),
-                buf_in.sink.data.eq(self.din_data.r),
-                buf_in.sink.k.eq(0),
-            ),
-        ]
+            self.writeable.status.eq(pak_wrp.sink.ack),
+            If(pak_wrp.sink.ack,pak_wrp.sink.stb.eq(0)),
+            If(self.data.re,
+                pak_wrp.sink.stb.eq(1),
+                pak_wrp.sink.data.eq(self.data.r),
 
-        self.comb += buf_in.source.connect(pak_wrp.sink),
-        self.source = pak_wrp.source
+                pak_wrp.sink.k.eq(0),
+                If(len == self.len.storage,
+                    pak_wrp.sink.eop.eq(1),
+                    len.eq(len.reset),
+                ).Else(
+                    pak_wrp.sink.eop.eq(0),
+                    len.eq(len + 1),
+                ),
+            )
+        ]