morgan/artiq-zynq
1
0
Fork 0
forked from M-Labs/artiq-zynq
Code Pull Requests Activity

upconn FW: update csr

Browse Source
This commit is contained in:
morgan 2025-01-14 14:21:50 +08:00
parent f87e498994
commit abcfd37487
1 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/libboard_artiq/src/cxp_upconn.rs
View File

@ -15,13 +15,13 @@ pub fn tx_test(channel: u8, timer: &mut GlobalTimer) {
let channel = channel as usize; let channel = channel as usize;
unsafe { unsafe {
(CXP[channel].upconn_trig_delay_write)(0x86); (CXP[channel].tx_trig_delay_write)(0x86);
(CXP[channel].upconn_linktrigger_write)(0x00); (CXP[channel].tx_linktrigger_write)(0x00);
// DEBUG: prepare the packet before tx enable to avoid overhead // DEBUG: prepare the packet before tx enable to avoid overhead
preload_tx_packet( preload_tx_packet(
channel as u8, channel as u8,
&cxp_proto::UpConnPacket::CtrlRead { &cxp_proto::TXPacket::CtrlRead {
tag: None, tag: None,
addr: 0, addr: 0,
length: 4, length: 4,
@ -32,8 +32,8 @@ pub fn tx_test(channel: u8, timer: &mut GlobalTimer) {
timer.delay_us(1); timer.delay_us(1);
// DEBUG: send ctrl packet or test // DEBUG: send ctrl packet or test
(CXP[channel].upconn_bootstrap_tx_write)(1); (CXP[channel].tx_bootstrap_tx_write)(1);
(CXP[channel].upconn_bootstrap_tx_testseq_write)(1); (CXP[channel].tx_bootstrap_tx_testseq_write)(1);
// DEBUG: Trigger packet (NOTE: disconnected in Gateware) // DEBUG: Trigger packet (NOTE: disconnected in Gateware)
// (CXP[channel].upconn_trig_stb_write)(1); // send trig // (CXP[channel].upconn_trig_stb_write)(1); // send trig
@ -74,10 +74,10 @@ pub fn tx_test(channel: u8, timer: &mut GlobalTimer) {
} }
} }
fn preload_tx_packet(channel: u8, packet: &cxp_proto::UpConnPacket) { fn preload_tx_packet(channel: u8, packet: &cxp_proto::TXPacket) {
let channel = channel as usize; let channel = channel as usize;
unsafe { unsafe {
while (CXP[channel].upconn_bootstrap_tx_busy_read)() == 1 {} while (CXP[channel].tx_bootstrap_tx_busy_read)() == 1 {}
let ptr = CXP_MEM[channel].base as *mut u32; let ptr = CXP_MEM[channel].base as *mut u32;
let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN)); let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN));
@ -86,6 +86,6 @@ fn preload_tx_packet(channel: u8, packet: &cxp_proto::UpConnPacket) {
println!("TX MEM after writing"); println!("TX MEM after writing");
cxp_proto::print_packet(&writer.get_ref()[0..40]); cxp_proto::print_packet(&writer.get_ref()[0..40]);
(CXP[channel].upconn_bootstrap_tx_word_len_write)(writer.position() as u16 / 4); (CXP[channel].tx_bootstrap_tx_word_len_write)(writer.position() as u16 / 4);
} }
} }