forked from M-Labs/artiq-zynq
cxp downconn fw: change to 40bits
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49d5cad5fd
commit
aa128e1467
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@ -1,6 +1,6 @@
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use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
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use libboard_zynq::{println, timer::GlobalTimer};
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use log::{error, info};
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use log::info;
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// use log::info;
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use crate::pl::csr;
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@ -68,7 +68,7 @@ fn loopback_testing(timer: &mut GlobalTimer, data: u8, control_bit: u8) {
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info!("waiting for rx to align...");
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// timer.delay_us(50_000);
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// while csr::cxp::downconn_rx_ready_read() != 1 {}
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info!("rx ready!");
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// info!("rx ready!");
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// println!("0xA8 = {:#06x}", read(0x62));
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// write(0x62, 0x001A);
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@ -76,27 +76,51 @@ fn loopback_testing(timer: &mut GlobalTimer, data: u8, control_bit: u8) {
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// for _ in 0..20 {
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loop {
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// NOTE: raw data
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let data0 = csr::cxp::downconn_rxdata_0_read();
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// let data1 = csr::cxp::downconn_rxdata_1_read();
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let rxready = csr::cxp::downconn_rx_ready_read();
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let data1 = csr::cxp::downconn_rxdata_1_read();
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// let rxready = csr::cxp::downconn_rx_ready_read();
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// timer.delay_us(100);
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// if data0 == 0b0101111100 || data0 == 0b1010000011 {
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// println!(
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// "data[0] = {:#012b} comma = {} | rx ready = {}",
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// data0,
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// data0 == 0b0101111100 || data0 == 0b1010000011,
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// rxready,
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// );
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// timer.delay_us(1_000_000);
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if data0 == 0b0101111100 || data0 == 0b1010000011 {
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println!(
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"data[0] = {:#012b} comma = {} | rx ready = {}",
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data0,
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data0 == 0b0101111100 || data0 == 0b1010000011,
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rxready,
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);
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// } else if data0 == 0b1001111100 || data0 == 0b0110000011 {
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// println!(
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// "data[0] = {:#012b} K28.1 | rx ready = {}",
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// data0,
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// rxready,
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// );
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// timer.delay_us(1_000_000);
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// } else {
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// println!(
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// "data[0] = {:#012b} | rx ready = {}",
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// data0,
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// rxready,
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// );
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// timer.delay_us(1_000_000);
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// }
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println!("0b{:010b}{:010b}", data0, data1);
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timer.delay_us(1_000_000);
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}
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// NOTE:decode data
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// let data0_decoded = csr::cxp::downconn_decoded_data_0_read();
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// let data0_k = csr::cxp::downconn_decoded_k_0_read();
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// let data1_decoded = csr::cxp::downconn_decoded_data_1_read();
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// let data1_k = csr::cxp::downconn_decoded_k_1_read();
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// println!(
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// "decoded_data[0] = {:#04x} decoded_k[0] = {:#b} decoded_data[1] = {:#04x} decoded_k[1] = {:#b}",
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// csr::cxp::downconn_decoded_data_0_read(),
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// csr::cxp::downconn_decoded_k_0_read(),
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// csr::cxp::downconn_decoded_data_1_read(),
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// csr::cxp::downconn_decoded_k_1_read(),
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// data0_decoded,
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// data0_k,
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// data1_decoded,
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// data1_k,
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// );
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// timer.delay_us(1_000_000);
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}
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}
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}
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@ -148,9 +172,7 @@ pub mod CXP_GTX {
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let settings = txusrclk::get_txusrclk_config(speed);
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txusrclk::setup(timer, settings);
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// TODO: set QPLL_FBDIV via DRP
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change_qpll_settings(speed);
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change_cdr_cfg(speed);
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unsafe {
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@ -169,27 +191,28 @@ pub mod CXP_GTX {
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fn change_qpll_settings(speed: CXP_SPEED) {
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match speed {
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CXP_SPEED::CXP_12 => {
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error!("CXP 12.5Gbps is not supported on zc706");
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panic!("CXP 12.5Gbps is not supported on zc706");
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}
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_ => {}
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}
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// DEBUG: this switches between High and Low band VCO
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// this switches between High and Low band VCO
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// NOT needed if VCO can do 12.5GHz
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let qpll_cfg_reg0 = match speed {
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// DEBUG: for ZC706 QPLL VCO that cannot go up to 12.5GHz
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// NOTE: for ZC706 QPLL VCO that cannot go up to 12.5GHz
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CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0181,
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CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x01C1,
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};
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// Change QPLL_REFCLK_DIV
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let qpll_div_reg0 = match speed {
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// DEBUG: for ZC706 QPLL VCO that cannot go up to 12.5GHz
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// NOTE: for ZC706 QPLL VCO that cannot go up to 12.5GHz
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CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x8068,
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CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0068,
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};
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// Change QPLL_FBDIV
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let qpll_div_reg1 = match speed {
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// DEBUG: for ZC706 QPLL VCO that cannot go up to 12.5GHz
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CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0120,
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CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0170,
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};
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@ -207,13 +230,13 @@ pub mod CXP_GTX {
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println!("0x36 = {:#018b}", qpll_read(0x36));
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let divider = match speed {
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// DEBUG: for ZC706 QPLL VCO that cannot go up to 12.5GHz
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// NOTE: for ZC706 QPLL VCO that cannot go up to 12.5GHz
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CXP_SPEED::CXP_1 => 0b100, // Divided by 8
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CXP_SPEED::CXP_2 => 0b011, // Divided by 4
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CXP_SPEED::CXP_5 | CXP_SPEED::CXP_3 => 0b010, // Divided by 2
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CXP_SPEED::CXP_10 | CXP_SPEED::CXP_6 => 0b001, // Divided by 1
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CXP_SPEED::CXP_12 => 0b000,
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// DEBUG: for ZC706 QPLL VCO that go up to 12.5GHz
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// NOTE: for ZC706 QPLL VCO that go up to 12.5GHz
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// CXP_SPEED::CXP_1 => 0b100, // Divided by 8
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// CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0b011, // Divided by 4
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// CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0b010, // Divided by 2
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@ -227,8 +250,40 @@ pub mod CXP_GTX {
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}
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fn change_cdr_cfg(speed: CXP_SPEED) {
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// NOTE: for ZC706 QPLL VCO that cannot go up to 12.5GHz
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let cdr_cfg = match speed {
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CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => {
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// Divided by 8
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CXP_SPEED::CXP_1 => {
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RX_CDR_CFG {
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cfg_reg0: 0x0020, //0x0A8
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cfg_reg1: 0x1008, //0x0A9
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cfg_reg2: 0x23FF, //0x0AA
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cfg_reg3: 0x0000, //0x0AB
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cfg_reg4: 0x0003, //0x0AC
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}
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}
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// Divided by 4
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CXP_SPEED::CXP_2 => {
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RX_CDR_CFG {
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cfg_reg0: 0x0020, //0x0A8
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cfg_reg1: 0x1010, //0x0A9
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cfg_reg2: 0x23FF, //0x0AA
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cfg_reg3: 0x0000, //0x0AB
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cfg_reg4: 0x0003, //0x0AC
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}
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}
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// Divided by 2
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CXP_SPEED::CXP_3 | CXP_SPEED::CXP_5 => {
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RX_CDR_CFG {
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cfg_reg0: 0x0020, //0x0A8
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cfg_reg1: 0x1020, //0x0A9
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cfg_reg2: 0x23FF, //0x0AA
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cfg_reg3: 0x0000, //0x0AB
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cfg_reg4: 0x0003, //0x0AC
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}
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}
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// Divided by 1
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CXP_SPEED::CXP_6 => {
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RX_CDR_CFG {
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cfg_reg0: 0x0020, //0x0A8
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cfg_reg1: 0x1040, //0x0A9
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@ -237,6 +292,7 @@ pub mod CXP_GTX {
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cfg_reg4: 0x0003, //0x0AC
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}
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}
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// Divided by 1
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CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => {
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RX_CDR_CFG {
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cfg_reg0: 0x0020, //0x0A8
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@ -431,6 +487,23 @@ pub mod txusrclk {
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pub fn get_txusrclk_config(speed: CXP_SPEED) -> PLLSetting {
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match speed {
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CXP_SPEED::CXP_1 => {
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// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 32
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// TXUSRCLK=62.5MHz
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PLLSetting {
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clkout0_reg1: 0x1410, //0x08
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clkout0_reg2: 0x0000, //0x09
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clkfbout_reg1: 0x1104, //0x14
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clkfbout_reg2: 0x0000, //0x15
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div_reg: 0x1041, //0x16
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lock_reg1: 0x03e8, //0x18
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lock_reg2: 0x5801, //0x19
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lock_reg3: 0xdbe9, //0x1A
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power_reg: 0x0000, //0x28
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filt_reg1: 0x9808, //0x4E
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filt_reg2: 0x9100, //0x4F
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}
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}
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CXP_SPEED::CXP_2 => {
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// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 16
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// TXUSRCLK=62.5MHz
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PLLSetting {
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@ -447,7 +520,24 @@ pub mod txusrclk {
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filt_reg2: 0x9100, //0x4F
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}
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}
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CXP_SPEED::CXP_2 => {
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CXP_SPEED::CXP_3 => {
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// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 16
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// TXUSRCLK=78.125MHz
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PLLSetting {
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clkout0_reg1: 0x1208, //0x08
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clkout0_reg2: 0x0000, //0x09
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clkfbout_reg1: 0x1145, //0x14
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clkfbout_reg2: 0x0000, //0x15
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div_reg: 0x1041, //0x16
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lock_reg1: 0x03e8, //0x18
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lock_reg2: 0x7001, //0x19
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lock_reg3: 0xf3e9, //0x1A
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power_reg: 0x0000, //0x28
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filt_reg1: 0x9908, //0x4E
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filt_reg2: 0x1900, //0x4F
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}
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}
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CXP_SPEED::CXP_5 => {
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// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
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// TXUSRCLK=125MHz
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PLLSetting {
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@ -464,9 +554,9 @@ pub mod txusrclk {
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filt_reg2: 0x9100, //0x4F
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}
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}
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CXP_SPEED::CXP_3 => {
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CXP_SPEED::CXP_6 => {
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// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
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// TXUSRCLK=125MHz
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// TXUSRCLK=156.25MHz
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PLLSetting {
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clkout0_reg1: 0x1104, //0x08
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clkout0_reg2: 0x0000, //0x09
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@ -481,7 +571,7 @@ pub mod txusrclk {
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filt_reg2: 0x1900, //0x4F
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}
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}
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CXP_SPEED::CXP_5 => {
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CXP_SPEED::CXP_10 => {
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// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
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// TXUSRCLK=250MHz
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PLLSetting {
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@ -498,7 +588,7 @@ pub mod txusrclk {
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filt_reg2: 0x9100, //0x4F
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}
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}
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CXP_SPEED::CXP_6 => {
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CXP_SPEED::CXP_12 => {
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// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
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// TXUSRCLK=312.5MHz
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PLLSetting {
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@ -515,40 +605,6 @@ pub mod txusrclk {
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filt_reg2: 0x1900, //0x4F
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}
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}
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CXP_SPEED::CXP_10 => {
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// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 2
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// TXUSRCLK=500MHz
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PLLSetting {
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clkout0_reg1: 0x1041, //0x08
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clkout0_reg2: 0x0000, //0x09
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clkfbout_reg1: 0x1104, //0x14
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clkfbout_reg2: 0x0000, //0x15
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div_reg: 0x1041, //0x16
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lock_reg1: 0x03e8, //0x18
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lock_reg2: 0x5801, //0x19
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lock_reg3: 0xdbe9, //0x1A
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power_reg: 0x0000, //0x28
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filt_reg1: 0x9808, //0x4E
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filt_reg2: 0x9100, //0x4F
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}
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}
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CXP_SPEED::CXP_12 => {
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// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 2
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// TXUSRCLK=625MHz
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PLLSetting {
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clkout0_reg1: 0x1041, //0x08
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clkout0_reg2: 0x0000, //0x09
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clkfbout_reg1: 0x1145, //0x14
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clkfbout_reg2: 0x0000, //0x15
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div_reg: 0x1041, //0x16
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lock_reg1: 0x03e8, //0x18
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lock_reg2: 0x7001, //0x19
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lock_reg3: 0xf3e9, //0x1A
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power_reg: 0x0000, //0x28
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filt_reg1: 0x9908, //0x4E
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filt_reg2: 0x1900, //0x4F
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}
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}
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}
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}
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}
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