diff --git a/sim_pipeline.py b/sim_pipeline.py
index f0f7853..ba16899 100644
--- a/sim_pipeline.py
+++ b/sim_pipeline.py
@@ -24,15 +24,19 @@ class EOP_Marker(Module):
             self.sink.ack.eq(~self.source.stb | self.source.ack),
             self.source.eop.eq(~self.sink.stb & last_stb),
         ]
+
 class Streams_Crossbar(Module):
     def __init__(self, downconn_sources, stream_sinks):
         n_downconn = len(downconn_sources)
+        self.active_conn= C(n_downconn) 
+        # TODO: change self.active_conns to signal and link it to rx_ready of GTX lanes
+
+        # # #
+
         self.submodules.mux = mux = stream.Multiplexer(word_layout_dchar, n_downconn)
 
-        for i, c in enumerate(downconn_sources):
-            self.comb += [
-                c.source.connect(getattr(mux, "sink"+str(i)))
-            ]
+        for i, downconn in enumerate(downconn_sources):
+            self.comb += downconn.source.connect(getattr(mux, "sink"+str(i)))
 
         self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
 
@@ -54,11 +58,15 @@ class Streams_Crossbar(Module):
             ),
         )
 
+        # Section 9.5.5 (CXP-001-2021)
+        # When Multiple connections are active, stream packets are transmitted in
+        # ascending order of Connection ID. And one connection shall be transmitting data at a time.
         read_mask = Signal(max=n_downconn)
         self.comb += mux.sel.eq(read_mask)
         fsm.act(
             "SWITCH_CONN",
-            If(read_mask == n_downconn - 1,
+            # assuming downconn_sources have ascending Connection ID 
+            If(read_mask == self.active_conn - 1,
                 NextValue(read_mask, read_mask.reset),
             ).Else(
                 NextValue(read_mask, read_mask + 1),