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phys FW: update csr

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morgan 2025-01-14 14:22:21 +08:00
parent ab3620bac4
commit a731b23e03
1 changed files with 9 additions and 12 deletions
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21
src/libboard_artiq/src/cxp_phys.rs
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@ -70,10 +70,7 @@ mod rx {
info!("waiting for rx setup..."); info!("waiting for rx setup...");
timer.delay_us(50_000); timer.delay_us(50_000);
for ch in 0..CXP_CHANNELS { for ch in 0..CXP_CHANNELS {
info!( info!("rx_phaligndone = {}", (CXP[ch as usize].rx_rxinit_phaligndone_read)());
"rx_phaligndone = {}",
(CXP[ch as usize].downconn_rxinit_phaligndone_read)()
);
} }
} }
} }
@ -180,20 +177,20 @@ mod rx {
fn gtx_read(channel: u8, address: u16) -> u16 { fn gtx_read(channel: u8, address: u16) -> u16 {
let channel = channel as usize; let channel = channel as usize;
unsafe { unsafe {
(CXP[channel].downconn_gtx_daddr_write)(address); (CXP[channel].rx_gtx_daddr_write)(address);
(CXP[channel].downconn_gtx_dread_write)(1); (CXP[channel].rx_gtx_dread_write)(1);
while (CXP[channel].downconn_gtx_dready_read)() != 1 {} while (CXP[channel].rx_gtx_dready_read)() != 1 {}
(CXP[channel].downconn_gtx_dout_read)() (CXP[channel].rx_gtx_dout_read)()
} }
} }
fn gtx_write(channel: u8, address: u16, value: u16) { fn gtx_write(channel: u8, address: u16, value: u16) {
let channel = channel as usize; let channel = channel as usize;
unsafe { unsafe {
(CXP[channel].downconn_gtx_daddr_write)(address); (CXP[channel].rx_gtx_daddr_write)(address);
(CXP[channel].downconn_gtx_din_write)(value); (CXP[channel].rx_gtx_din_write)(value);
(CXP[channel].downconn_gtx_din_stb_write)(1); (CXP[channel].rx_gtx_din_stb_write)(1);
while (CXP[channel].downconn_gtx_dready_read)() != 1 {} while (CXP[channel].rx_gtx_dready_read)() != 1 {}
} }
} }