cxp downconn fw: add qpll drg config

src/libboard_artiq/src/cxp_downconn.rs

@@ -1,7 +1,8 @@
 use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
 use libboard_zynq::{println, timer::GlobalTimer};
-use log::info;
+use log::{error, info};
 
+// use log::info;
 use crate::pl::csr;
 
 pub struct CXP_DownConn_Settings {
@@ -166,11 +167,57 @@ pub mod CXP_GTX {
     }
 
     fn change_qpll_settings(speed: CXP_SPEED) {
+        match speed {
+            CXP_SPEED::CXP_12 => {
+                error!("CXP 12.5Gbps is not supported on zc706");
+            }
+            _ => {}
+        }
+
+        // DEBUG: this switches between High and Low band VCO
+        // NOT needed if VCO can do 12.5GHz
+        let qpll_cfg_reg0 = match speed {
+            // DEBUG: for ZC706 QPLL VCO that cannot go up to 12.5GHz
+            CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0181,
+            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x01C1,
+        };
+
+        let qpll_div_reg0 = match speed {
+            // DEBUG: for ZC706 QPLL VCO that cannot go up to 12.5GHz
+            CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x8068,
+            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0068,
+        };
+
+        let qpll_div_reg1 = match speed {
+            // DEBUG: for ZC706 QPLL VCO that cannot go up to 12.5GHz
+            CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0120,
+            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0170,
+        };
+
+        println!("0x32 = {:#018b}", qpll_read(0x32));
+        qpll_write(0x32, qpll_cfg_reg0);
+        println!("0x32 = {:#018b}", qpll_read(0x32));
+
+        println!("0x33 = {:#018b}", qpll_read(0x33));
+        qpll_write(0x33, qpll_div_reg0);
+        println!("0x33 = {:#018b}", qpll_read(0x33));
+
+        println!("0x36 = {:#018b}", qpll_read(0x36));
+        qpll_write(0x36, qpll_div_reg1);
+        println!("0x36 = {:#018b}", qpll_read(0x36));
+
         let divider = match speed {
-            CXP_SPEED::CXP_1 => 0b100,                      // Divided by 8
+            // DEBUG: for ZC706 QPLL VCO that cannot go up to 12.5GHz
-            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0b011,   // Divided by 4
+            CXP_SPEED::CXP_1 => 0b100,                     // Divided by 8
-            CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0b010,   // Divided by 2
+            CXP_SPEED::CXP_2 => 0b011,                     // Divided by 4
-            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0b001, // Divided by 1
+            CXP_SPEED::CXP_5 | CXP_SPEED::CXP_3 => 0b010,  // Divided by 2
+            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_6 => 0b001, // Divided by 1
+            CXP_SPEED::CXP_12 => 0b000,
+            // DEBUG: for ZC706 QPLL VCO that go up to 12.5GHz
+            // CXP_SPEED::CXP_1 => 0b100,                      // Divided by 8
+            // CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0b011,   // Divided by 4
+            // CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0b010,   // Divided by 2
+            // CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0b001, // Divided by 1
         };
 
         unsafe {
@@ -201,12 +248,14 @@ pub mod CXP_GTX {
             }
         };
 
-        println!("0x0AC = {}", read(0x0AC));
+        gtx_write(0x0A8, cdr_cfg.cfg_reg0);
-        write(0x0AC, cdr_cfg.cfg_reg4);
+        gtx_write(0x0A9, cdr_cfg.cfg_reg1);
-        println!("0x0AC = {}", read(0x0AC));
+        gtx_write(0x0AA, cdr_cfg.cfg_reg2);
+        gtx_write(0x0AB, cdr_cfg.cfg_reg3);
+        gtx_write(0x0AC, cdr_cfg.cfg_reg4);
     }
 
-    fn read(address: u16) -> u16 {
+    fn gtx_read(address: u16) -> u16 {
         // DEBUG: DRPCLK need to be on for a few cycle before accessing other DRP ports
         unsafe {
             csr::cxp::downconn_gtx_daddr_write(address);
@@ -216,7 +265,7 @@ pub mod CXP_GTX {
         }
     }
 
-    fn write(address: u16, value: u16) {
+    fn gtx_write(address: u16, value: u16) {
         // DEBUG: DRPCLK need to be on for a few cycle before accessing other DRP ports
         unsafe {
             csr::cxp::downconn_gtx_daddr_write(address);
@@ -225,6 +274,24 @@ pub mod CXP_GTX {
             while (csr::cxp::downconn_gtx_dready_read() != 1) {}
         }
     }
+
+    fn qpll_read(address: u8) -> u16 {
+        unsafe {
+            csr::cxp::downconn_qpll_daddr_write(address);
+            csr::cxp::downconn_qpll_dread_write(1);
+            while (csr::cxp::downconn_qpll_dready_read() != 1) {}
+            csr::cxp::downconn_qpll_dout_read()
+        }
+    }
+
+    fn qpll_write(address: u8, value: u16) {
+        unsafe {
+            csr::cxp::downconn_qpll_daddr_write(address);
+            csr::cxp::downconn_qpll_din_write(value);
+            csr::cxp::downconn_qpll_din_stb_write(1);
+            while (csr::cxp::downconn_qpll_dready_read() != 1) {}
+        }
+    }
 }
 
 pub mod txusrclk {