forked from M-Labs/artiq-zynq
cxp GW: add 8 ROI & cleanup
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@ -287,7 +287,7 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
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class CXP_Grabber(Module, AutoCSR):
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# optimal stream packet size is 2 KiB - Section 9.5.2 (CXP-001-2021)
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def __init__(self, host, roi_engine_count=2, res_width=16, count_width=31):
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def __init__(self, host, roi_engine_count=8, res_width=16, count_width=31):
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assert count_width <= 31
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self.crc_error_cnt = CSRStatus(16)
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@ -367,6 +367,8 @@ class CXP_Grabber(Module, AutoCSR):
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buffer.source.connect(stream2pix.sink),
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]
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# ROI engines config and count gating
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roi_engines = [cdr(ROI(stream2pix.pixel4x, count_width)) for _ in range(roi_engine_count)]
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self.submodules += roi_engines
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@ -378,25 +380,6 @@ class CXP_Grabber(Module, AutoCSR):
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roi_boundary.eq(self.config.o.data))
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self.specials += MultiReg(roi_boundary, target, "cxp_gt_rx")
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# roi_out = roi.out
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# update = Signal()
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# self.submodules.ps = ps = PulseSynchronizer("cxp_gt_rx", "sys")
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# self.sync.cxp_gt_rx += ps.i.eq(roi_out.update)
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# self.sync += update.eq(ps.o)
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# sentinel = 2**count_width
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# count_sys = Signal.like(roi_out.count)
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# self.specials += MultiReg(roi_out.count, count_sys),
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# self.sync.rio += [
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# # TODO: add gating
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# self.gate_data.i.stb.eq(update),
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# # without the slice, unspecified bits will be 1 for some reason
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# # i.e. data[count_wdith:] = 0b111111... when using data.eq(count_sys)
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# self.gate_data.i.data[:count_width].eq(count_sys),
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# ]
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self.submodules.synchronizer = synchronizer = CXP_Synchronizer(roi_engines)
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self.submodules.serializer = serializer = Serializer(synchronizer.update, synchronizer.counts, self.gate_data.i)
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