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cxp GW: refactor to combine rx/tx into phy

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morgan 2025-01-14 12:18:06 +08:00
parent 7af9cc2d02
commit a5d5471734
1 changed files with 17 additions and 9 deletions
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26
src/gateware/cxp.py
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@ -5,25 +5,33 @@ from misoc.interconnect.csr import *
from artiq.gateware.rtio import rtlink from artiq.gateware.rtio import rtlink
from cxp_downconn import CXP_DownConn_PHYS from cxp_downconn import CXP_DownConn_PHYS
from cxp_upconn import CXP_UpConn_PHYS from cxp_upconn import CXP_TXPHYs
from cxp_pipeline import * from cxp_pipeline import *
from cxp_frame_pipeline import * from cxp_frame_pipeline import *
from functools import reduce from functools import reduce
from operator import add from operator import add
from types import SimpleNamespace
class CXP_PHYS(Module, AutoCSR): class CXP_PHYS(Module, AutoCSR):
def __init__(self, refclk, upconn_pads, downconn_pads, sys_clk_freq, debug_sma, pmod_pads): def __init__(self, refclk, upconn_pads, downconn_pads, sys_clk_freq, debug_sma, pmod_pads):
assert len(upconn_pads) == len(downconn_pads) assert len(upconn_pads) == len(downconn_pads)
self.submodules.upconn = CXP_UpConn_PHYS(upconn_pads, sys_clk_freq, debug_sma, pmod_pads) self.submodules.tx = CXP_TXPHYs(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
self.submodules.downconn = CXP_DownConn_PHYS(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads) self.submodules.downconn = CXP_DownConn_PHYS(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
self.phys = []
for tx, rx in zip(self.tx.phys, self.downconn.rx_phys):
phy = SimpleNamespace()
phy.tx, phy.rx = tx, rx
self.phys.append(phy)
@FullMemoryWE() @FullMemoryWE()
class CXP_Interface(Module, AutoCSR): class CXP_Interface(Module, AutoCSR):
def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads): def __init__(self, phy, debug_sma, pmod_pads):
self.submodules.upconn = UpConn_Interface(upconn_phy, debug_sma, pmod_pads) self.submodules.upconn = UpConn_Interface(phy.tx, debug_sma, pmod_pads)
self.submodules.downconn = DownConn_Interface(downconn_phy, debug_sma, pmod_pads) self.submodules.downconn = DownConn_Interface(phy.rx, debug_sma, pmod_pads)
def get_tx_port(self): def get_tx_port(self):
return self.upconn.bootstrap.mem.get_port(write_capable=True) return self.upconn.bootstrap.mem.get_port(write_capable=True)
@ -49,8 +57,8 @@ class CXP_Interface(Module, AutoCSR):
return self.downconn return self.downconn
class CXP_Master(CXP_Interface): class CXP_Master(CXP_Interface):
def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads): def __init__(self, phy, debug_sma, pmod_pads):
CXP_Interface.__init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads) CXP_Interface.__init__(self, phy, debug_sma, pmod_pads)
nbit_trigdelay = 8 nbit_trigdelay = 8
nbit_linktrig = 1 nbit_linktrig = 1
@ -72,8 +80,8 @@ class CXP_Master(CXP_Interface):
# self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.n_rx), # self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.n_rx),
class CXP_Extension(CXP_Interface): class CXP_Extension(CXP_Interface):
def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads): def __init__(self, phy, debug_sma, pmod_pads):
CXP_Interface.__init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads) CXP_Interface.__init__(self, phy, debug_sma, pmod_pads)
class DownConn_Interface(Module, AutoCSR): class DownConn_Interface(Module, AutoCSR):