forked from M-Labs/artiq-zynq
wrpll runtime: reduce mmcm output jitter
rtio_clocking: update mmcm setting to use HIGH bandwidth
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parent
dcdad71909
commit
a597d0b8e2
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@ -278,8 +278,8 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
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lock_reg2: 0x7c01,
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lock_reg2: 0x7c01,
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lock_reg3: 0xffe9,
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lock_reg3: 0xffe9,
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power_reg: 0x9900,
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power_reg: 0x9900,
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filt_reg1: 0x0808,
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filt_reg1: 0x1008,
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filt_reg2: 0x0800,
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filt_reg2: 0x8800,
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},
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},
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false,
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false,
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),
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),
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@ -295,8 +295,8 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
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lock_reg2: 0x7c01,
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lock_reg2: 0x7c01,
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lock_reg3: 0xffe9,
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lock_reg3: 0xffe9,
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power_reg: 0x9900,
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power_reg: 0x9900,
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filt_reg1: 0x0808,
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filt_reg1: 0x9908,
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filt_reg2: 0x9800,
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filt_reg2: 0x8100,
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},
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},
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false,
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false,
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),
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),
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@ -312,8 +312,8 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
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lock_reg2: 0x7c01,
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lock_reg2: 0x7c01,
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lock_reg3: 0xffe9,
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lock_reg3: 0xffe9,
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power_reg: 0x9900,
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power_reg: 0x9900,
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filt_reg1: 0x0808,
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filt_reg1: 0x9108,
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filt_reg2: 0x9800,
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filt_reg2: 0x0100,
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},
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},
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false,
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false,
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),
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),
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@ -329,7 +329,7 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
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lock_reg2: 0x7001,
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lock_reg2: 0x7001,
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lock_reg3: 0xf3e9,
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lock_reg3: 0xf3e9,
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power_reg: 0x0100,
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power_reg: 0x0100,
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filt_reg1: 0x0808,
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filt_reg1: 0x9908,
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filt_reg2: 0x1100,
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filt_reg2: 0x1100,
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},
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},
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true,
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true,
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