forked from M-Labs/artiq-zynq
phys FW: update csr
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844f2dab70
commit
a4f6f0e4c5
@ -59,12 +59,12 @@ mod rx {
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pub fn setup(timer: &mut GlobalTimer) {
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unsafe {
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csr::cxp_phys::downconn_qpll_reset_write(1);
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csr::cxp_phys::rx_qpll_reset_write(1);
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info!("waiting for QPLL/CPLL to lock...");
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while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
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while csr::cxp_phys::rx_qpll_locked_read() != 1 {}
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info!("QPLL locked");
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csr::cxp_phys::downconn_gtx_start_init_write(1);
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csr::cxp_phys::rx_gtx_start_init_write(1);
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// DEBUG: printout
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info!("waiting for rx setup...");
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@ -84,12 +84,12 @@ mod rx {
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change_cdr_cfg(speed);
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unsafe {
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csr::cxp_phys::downconn_qpll_reset_write(1);
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csr::cxp_phys::rx_qpll_reset_write(1);
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info!("waiting for QPLL/CPLL to lock...");
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while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
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while csr::cxp_phys::rx_qpll_locked_read() != 1 {}
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info!("QPLL locked");
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csr::cxp_phys::downconn_gtx_restart_write(1);
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csr::cxp_phys::rx_gtx_restart_write(1);
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}
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}
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@ -200,19 +200,19 @@ mod rx {
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#[allow(dead_code)]
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fn qpll_read(address: u8) -> u16 {
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unsafe {
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csr::cxp_phys::downconn_qpll_daddr_write(address);
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csr::cxp_phys::downconn_qpll_dread_write(1);
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while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
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csr::cxp_phys::downconn_qpll_dout_read()
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csr::cxp_phys::rx_qpll_daddr_write(address);
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csr::cxp_phys::rx_qpll_dread_write(1);
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while csr::cxp_phys::rx_qpll_dready_read() != 1 {}
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csr::cxp_phys::rx_qpll_dout_read()
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}
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}
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fn qpll_write(address: u8, value: u16) {
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unsafe {
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csr::cxp_phys::downconn_qpll_daddr_write(address);
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csr::cxp_phys::downconn_qpll_din_write(value);
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csr::cxp_phys::downconn_qpll_din_stb_write(1);
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while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
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csr::cxp_phys::rx_qpll_daddr_write(address);
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csr::cxp_phys::rx_qpll_din_write(value);
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csr::cxp_phys::rx_qpll_din_stb_write(1);
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while csr::cxp_phys::rx_qpll_dready_read() != 1 {}
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}
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}
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}
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