morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

cxp upconn: separate 9bits data to data & k code

This commit is contained in:
morgan 2024-08-27 16:02:29 +08:00
parent 97bf7e72b7
commit a39c939a68
1 changed files with 5 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/gateware/cxp_upconn.py
View File

@ -218,13 +218,14 @@ class TxFIFOs(Module):
for i in range(nfifos):
cdr = ClockDomainsRenamer({"write": "sys", "read": "cxp_upconn"})
fifo = cdr(stream.AsyncFIFO([("data", 9)], fifo_depth))
fifo = cdr(stream.AsyncFIFO([("data", 8), ("k", 1)], fifo_depth))
setattr(self.submodules, "tx_fifo" + str(i), fifo)
self.sync += [
fifo.sink.stb.eq(self.sink_stb[i]),
self.sink_full[i].eq(fifo.sink.ack),
fifo.sink.data.eq(Cat(self.sink_data[i], self.sink_k[i])),
fifo.sink.data.eq(self.sink_data[i]),
fifo.sink.k.eq(self.sink_k[i]),
]
self.sync.cxp_upconn += [
@ -237,8 +238,8 @@ class TxFIFOs(Module):
),
non_empty[i].eq(fifo.source.stb),
self.source_data[i].eq(fifo.source.data[:8]),
self.source_k[i].eq(fifo.source.data[8]),
self.source_data[i].eq(fifo.source.data),
self.source_k[i].eq(fifo.source.k),
]
# FIFOs transmission priority