diff --git a/src/gateware/cxp_upconn.py b/src/gateware/cxp_upconn.py
index e69528b..ce9b59b 100644
--- a/src/gateware/cxp_upconn.py
+++ b/src/gateware/cxp_upconn.py
@@ -218,13 +218,14 @@ class TxFIFOs(Module):
 
         for i in range(nfifos):
             cdr = ClockDomainsRenamer({"write": "sys", "read": "cxp_upconn"})
-            fifo = cdr(stream.AsyncFIFO([("data", 9)], fifo_depth))
+            fifo = cdr(stream.AsyncFIFO([("data", 8), ("k", 1)], fifo_depth))
             setattr(self.submodules, "tx_fifo" + str(i), fifo)
 
             self.sync += [
                 fifo.sink.stb.eq(self.sink_stb[i]),
                 self.sink_full[i].eq(fifo.sink.ack),
-                fifo.sink.data.eq(Cat(self.sink_data[i], self.sink_k[i])),
+                fifo.sink.data.eq(self.sink_data[i]),
+                fifo.sink.k.eq(self.sink_k[i]),
             ]
 
             self.sync.cxp_upconn += [
@@ -237,8 +238,8 @@ class TxFIFOs(Module):
                 ),
 
                 non_empty[i].eq(fifo.source.stb),
-                self.source_data[i].eq(fifo.source.data[:8]),
-                self.source_k[i].eq(fifo.source.data[8]),
+                self.source_data[i].eq(fifo.source.data),
+                self.source_k[i].eq(fifo.source.k),
             ]
 
         # FIFOs transmission priority