forked from M-Labs/artiq-zynq
pipeline GW: refactor test seq
pipeline GW: refactor test seq pipeline gw: reader clenaup pipeline GW: fix issue pipeline GW: cleanup
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@ -364,14 +364,14 @@ class Duplicated_Char_Decoder(Module):
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@FullMemoryWE()
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class Control_Packet_Reader(Module):
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def __init__(self, buffer_depth, nslot):
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self.packet_type = Signal(8)
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self.decode_err = Signal()
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self.buffer_err = Signal()
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self.test_err = Signal()
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self.test_pak = Signal()
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self.buffer_err = Signal()
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self.write_ptr = Signal(log2_int(nslot))
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self.read_ptr = Signal.like(self.write_ptr)
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self.test_err_cnt = Signal(16)
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self.test_pak_cnt = Signal(16)
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self.test_cnt_reset = Signal()
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# # #
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type = {
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@ -387,37 +387,44 @@ class Control_Packet_Reader(Module):
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self.source = stream.Endpoint(word_layout_dchar)
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# N buffers for firmware to read packet from
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self.specials.mem = mem = Memory(word_width, nslot*buffer_depth)
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self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
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buf_mem_we = Signal.like(mem_port.we)
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buf_mem_dat_w = Signal.like(mem_port.dat_w)
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buf_mem_adr = Signal.like(mem_port.adr)
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# Data packet parser
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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# buffered mem_port to improve timing
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self.sync += [
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mem_port.we.eq(buf_mem_we),
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mem_port.dat_w.eq(buf_mem_dat_w),
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mem_port.adr.eq(buf_mem_adr)
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]
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addr_nbits = log2_int(buffer_depth)
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addr = Signal(addr_nbits)
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cnt = Signal(max=0x100)
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self.comb += [
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buf_mem_adr[:addr_nbits].eq(addr),
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buf_mem_adr[addr_nbits:].eq(self.write_ptr),
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]
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# Data packet parser
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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NextValue(addr, addr.reset),
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NextValue(cnt, cnt.reset),
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self.sink.ack.eq(1),
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If((self.sink.stb & (self.sink.dchar == KCode["pak_start"]) & (self.sink.dchar_k == 1)),
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NextState("DECODE"),
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)
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)
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test_pak = Signal()
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buf_mem_we = Signal.like(mem_port.we)
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buf_mem_dat_w = Signal.like(mem_port.dat_w)
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buf_mem_adr = Signal.like(mem_port.adr)
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fsm.act("DECODE",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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Case(self.sink.dchar, {
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type["data_stream"]: NextState("STREAMING"),
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type["test_packet"]: [
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test_pak.eq(1),
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self.test_pak.eq(1),
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NextState("VERIFY_TEST_PATTERN"),
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],
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type["control_ack_no_tag"]:[
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@ -463,64 +470,28 @@ class Control_Packet_Reader(Module):
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# Section 9.9.1 (CXP-001-2021)
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# the received test data packet (0x00, 0x01 ... 0xFF)
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# need to be compared against the local test sequence generator
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# TODO: improve this to avoid tight setup/hold time
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test_err = Signal()
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cnt_bytes = [Signal(char_width, reset=i) for i in range(4)]
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fsm.act("VERIFY_TEST_PATTERN",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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If(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
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[NextValue(cnt, cnt.reset) for cnt in cnt_bytes],
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NextState("IDLE"),
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).Else(
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If(self.sink.data[:8] != cnt,
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test_err.eq(1),
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).Elif(self.sink.data[8:16] != cnt + 1,
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test_err.eq(1),
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).Elif(self.sink.data[16:24] != cnt + 2,
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test_err.eq(1),
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).Elif(self.sink.data[24:] != cnt + 3,
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test_err.eq(1),
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),
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If(cnt == 0xFC,
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NextValue(cnt, cnt.reset),
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).Else(
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NextValue(cnt, cnt + 4)
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)
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[
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If(self.sink.data[8 * i : 8 * (i + 1)] != cnt,
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self.test_err.eq(1),
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),
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If(cnt == 0xFC + i,
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NextValue(cnt, cnt.reset),
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).Else(NextValue(cnt, cnt + 4)),
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]
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for i, cnt in enumerate(cnt_bytes)
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)
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)
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)
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# TODO: move this out of this module
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self.sync += [
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If(self.test_cnt_reset,
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self.test_err_cnt.eq(self.test_err_cnt.reset),
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).Elif(test_err,
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self.test_err_cnt.eq(self.test_err_cnt + 1),
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),
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If(self.test_cnt_reset,
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self.test_pak_cnt.eq(self.test_pak_cnt.reset),
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).Elif(test_pak,
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self.test_pak_cnt.eq(self.test_pak_cnt + 1),
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)
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]
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# buffered mem_port to improve timing
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self.sync += [
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mem_port.we.eq(buf_mem_we),
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mem_port.dat_w.eq(buf_mem_dat_w),
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mem_port.adr.eq(buf_mem_adr)
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]
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# TODO: move write_ptr_sys out of this module
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write_ptr = Signal(log2_int(nslot))
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self.write_ptr_sys = Signal.like(write_ptr)
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self.specials += MultiReg(write_ptr, self.write_ptr_sys),
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self.comb += [
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buf_mem_adr[:addr_nbits].eq(addr),
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buf_mem_adr[addr_nbits:].eq(write_ptr),
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]
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fsm.act("LOAD_BUFFER",
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buf_mem_we.eq(0),
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@ -535,21 +506,22 @@ class Control_Packet_Reader(Module):
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If(addr == buffer_depth - 1,
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# discard the packet
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self.buffer_err.eq(1),
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NextValue(addr, addr.reset),
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NextState("IDLE"),
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)
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)
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)
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)
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self.read_ptr_rx = Signal.like(write_ptr)
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fsm.act("MOVE_BUFFER_PTR",
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self.sink.ack.eq(0),
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If(write_ptr + 1 == self.read_ptr_rx,
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If(self.write_ptr + 1 == self.read_ptr,
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# if next one hasn't been read, overwrite the current buffer when new packet comes in
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self.buffer_err.eq(1),
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).Else(
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NextValue(write_ptr, write_ptr + 1),
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NextValue(self.write_ptr, self.write_ptr + 1),
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),
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NextValue(addr, addr.reset),
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NextState("IDLE"),
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)
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