From a358f1c930950051df54240cf6930d544f1abcb2 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Tue, 3 Sep 2024 11:36:27 +0800
Subject: [PATCH] cxp pipeline: add code source

---
 src/gateware/cxp_pipeline.py | 74 +++++++++++++++++++++++++++++-------
 1 file changed, 61 insertions(+), 13 deletions(-)

diff --git a/src/gateware/cxp_pipeline.py b/src/gateware/cxp_pipeline.py
index 4812717..0d9dd75 100644
--- a/src/gateware/cxp_pipeline.py
+++ b/src/gateware/cxp_pipeline.py
@@ -6,11 +6,54 @@ from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCI
 def K(x, y):
     return ((y << 5) | x)
 
+class Code_Source(Module):
+    def __init__(self, layout, counts=4):
+
+        self.source = stream.Endpoint(layout)
+        self.stb = Signal()
+        self.data = Signal.like(self.source.data)
+        self.k = Signal.like(self.source.k)
+
+        # # #
+
+        cnt = Signal(max=counts)
+        clr_cnt = Signal()
+        inc_cnt = Signal()
+
+        self.sync += [
+            If(clr_cnt,
+                cnt.eq(cnt.reset),
+            ).Elif(inc_cnt,
+                cnt.eq(cnt + 1),
+            )
+        ]
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        
+        fsm.act("IDLE",
+            clr_cnt.eq(1),
+            If(self.stb,
+               NextState("WRITE")
+            )
+        )
+
+        fsm.act("WRITE",
+            self.source.stb.eq(1),
+            self.source.data.eq(self.data),
+            self.source.k.eq(self.k),
+            If(cnt == counts - 1,
+                self.source.eop.eq(1),
+                If(self.source.ack, NextState("IDLE"))
+            ).Else(
+                inc_cnt.eq(self.source.ack)
+            )
+        )
+
 class Trigger_ACK(Module):
     def __init__(self, layout):
         self.ack = Signal()
 
-        self.source = source = stream.Endpoint(layout)
+        self.source = stream.Endpoint(layout)
 
         # # #
 
@@ -39,26 +82,26 @@ class Trigger_ACK(Module):
         )
 
         fsm.act("WRITE_ACK0",
-            source.stb.eq(1),
-            source.data.eq(K(28, 6)),
-            source.k.eq(1),
+            self.source.stb.eq(1),
+            self.source.data.eq(K(28, 6)),
+            self.source.k.eq(1),
             If(cnt == 3,
                 clr_cnt.eq(1),
-                If(source.ack, NextState("WRITE_ACK1"))
+                If(self.source.ack, NextState("WRITE_ACK1"))
             ).Else(
-                inc_cnt.eq(source.ack)
+                inc_cnt.eq(self.source.ack)
             )
         )
 
         fsm.act("WRITE_ACK1",
-            source.stb.eq(1),
-            source.data.eq(0x01),
-            source.k.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(0x01),
+            self.source.k.eq(0),
             If(cnt == 3,
-                source.eop.eq(1),
-                If(source.ack, NextState("IDLE"))
+                self.source.eop.eq(1),
+                If(self.source.ack, NextState("IDLE"))
             ).Else(
-                inc_cnt.eq(source.ack)
+                inc_cnt.eq(self.source.ack)
             )
         )
 
@@ -74,7 +117,12 @@ class Code_Inserter(Module):
 
         # # #
 
-        cnt = Signal(max=counts)
+        assert counts > 0
+
+        # TODO: make this cleaner
+        # FIX this to make it work for counts = 1
+
+        cnt = Signal() if counts == 1 else Signal(max=counts)
         clr_cnt = Signal()
         inc_cnt = Signal()