forked from M-Labs/artiq-zynq
cxp pipeline: packet handling pipeline
tx pipeline: add CRC32 inserter tx pipeline: add start & end of packet code inserter tx pipeline: add packet wrapper for start & stop packet indication tx pipeline: add code source for trigger & trigger ack packet tx pipeline: add packet for trigger & trigger ack tx pipeline: add test packet generator tx pipeline: add tx_command_packet for firmware tx command packet: add dma to store control packet rx pipeline: add reciever path rx pipeline: add duplicate char decoder rx pipeline: add trig ack checker rx pipeline: add packet decoder decoder: add test packet checher decoder: add packet DMA
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726
src/gateware/cxp_pipeline.py
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726
src/gateware/cxp_pipeline.py
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@ -0,0 +1,726 @@
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from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect.stream import Endpoint, SyncFIFO
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from functools import reduce
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from itertools import combinations
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from operator import or_, and_
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char_width = 8
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char_layout = [("data", char_width), ("k", char_width//8)]
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word_width = 32
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word_layout = [("data", word_width), ("k", word_width//8)]
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word_layout_dchar = [
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("data", word_width),
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("k", word_width//8),
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("dchar", char_width),
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("dchar_k", char_width//8),
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]
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def K(x, y):
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return ((y << 5) | x)
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def switch_endianness(s):
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assert len(s) % 8 == 0
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char = [s[i*8:(i+1)*8] for i in range(len(s)//8)]
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return Cat(char[::-1])
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KCode = {
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"pak_start" : C(K(27, 7), char_width),
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"io_ack" : C(K(28, 6), char_width),
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"trig_indic_28_2" : C(K(28, 2), char_width),
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"stream_marker" : C(K(28, 3), char_width),
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"trig_indic_28_4" : C(K(28, 4), char_width),
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"pak_end" : C(K(29, 7), char_width),
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"idle_comma" : C(K(28, 5), char_width),
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"idle_alignment" : C(K(28, 1), char_width),
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}
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class Packet_Wrapper(Module):
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def __init__(self):
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self.sink = Endpoint(word_layout)
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self.source = Endpoint(word_layout)
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# # #
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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self.sink.ack.eq(0),
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NextState("INSERT_HEADER"),
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)
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)
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fsm.act("INSERT_HEADER",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_start"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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If(self.source.ack, NextState("COPY")),
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)
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fsm.act("COPY",
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self.sink.connect(self.source),
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self.source.eop.eq(0),
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If(self.sink.stb & self.sink.eop & self.source.ack,
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NextState("INSERT_FOOTER"),
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),
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)
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fsm.act("INSERT_FOOTER",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_end"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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self.source.eop.eq(1),
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If(self.source.ack, NextState("IDLE")),
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)
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class Trigger_Inserter(Module):
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def __init__(self):
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self.stb = Signal()
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self.delay = Signal(char_width)
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self.linktrig_mode = Signal()
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# # #
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self.sink = Endpoint(char_layout)
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self.source = Endpoint(char_layout)
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# Table 15 & 16 (CXP-001-2021)
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# Send [K28.2, K28.4, K28.4] or [K28.4, K28.2, K28.2] and 3x delay as trigger packet
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trig_packet = [Signal(char_width), Signal(char_width), Signal(char_width), self.delay, self.delay, self.delay]
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trig_packet_k = [1, 1, 1, 0, 0, 0]
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self.comb += [
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If(self.linktrig_mode,
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trig_packet[0].eq(KCode["trig_indic_28_4"]),
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trig_packet[1].eq(KCode["trig_indic_28_2"]),
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trig_packet[2].eq(KCode["trig_indic_28_2"]),
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).Else(
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trig_packet[0].eq(KCode["trig_indic_28_2"]),
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trig_packet[1].eq(KCode["trig_indic_28_4"]),
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trig_packet[2].eq(KCode["trig_indic_28_4"]),
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),
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]
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self.submodules.fsm = fsm = FSM(reset_state="COPY")
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cnt = Signal(max=6)
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fsm.act("COPY",
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NextValue(cnt, cnt.reset),
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self.sink.connect(self.source),
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If(self.stb, NextState("WRITE_TRIG"))
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)
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fsm.act("WRITE_TRIG",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Array(trig_packet)[cnt]),
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self.source.k.eq(Array(trig_packet_k)[cnt]),
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If(self.source.ack,
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If(cnt == 5,
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NextState("COPY"),
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).Else(
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NextValue(cnt, cnt + 1),
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)
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)
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)
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class Idle_Word_Inserter(Module):
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def __init__(self):
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# Section 9.2.5 (CXP-001-2021)
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# Send K28.5, K28.1, K28.1, D21.5 as idle word
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self.submodules.fsm = fsm = FSM(reset_state="WRITE_IDLE")
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self.sink = Endpoint(word_layout)
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self.source = Endpoint(word_layout)
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# Section 9.2.5.1 (CXP-001-2021)
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# IDLE should be transmitter every 10000 words
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cnt = Signal(max=10000, reset=9999)
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fsm.act("WRITE_IDLE",
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self.source.stb.eq(1),
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self.source.data.eq(Cat(KCode["idle_comma"], KCode["idle_alignment"], KCode["idle_alignment"], C(0xB5, char_width))),
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self.source.k.eq(Cat(1, 1, 1, 0)),
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self.sink.ack.eq(1),
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If(self.sink.stb,
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self.sink.ack.eq(0),
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If(self.source.ack,
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NextValue(cnt, cnt.reset),
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NextState("COPY"),
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)
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),
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)
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fsm.act("COPY",
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self.sink.connect(self.source),
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# increment when uphas data and got ack
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If(self.sink.stb & self.source.ack, NextValue(cnt, cnt - 1)),
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If((( (~self.sink.stb) | (self.sink.eop) | (cnt == 0) ) & self.source.ack), NextState("WRITE_IDLE"))
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)
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class Trigger_ACK_Inserter(Module):
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def __init__(self):
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self.stb = Signal()
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# # #
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# Section 9.3.2 (CXP-001-2021)
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# Send 4x K28.6 and 4x 0x01 as trigger packet ack
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self.submodules.fsm = fsm = FSM(reset_state="COPY")
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self.sink = Endpoint(word_layout)
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self.source = Endpoint(word_layout)
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fsm.act("COPY",
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self.sink.connect(self.source),
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If(self.stb, NextState("WRITE_ACK0"))
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)
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fsm.act("WRITE_ACK0",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["io_ack"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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If(self.source.ack, NextState("WRITE_ACK1")),
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)
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fsm.act("WRITE_ACK1",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(C(0x01, char_width), 4)),
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self.source.k.eq(Replicate(0, 4)),
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If(self.source.ack, NextState("COPY")),
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)
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@FullMemoryWE()
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class Command_Test_Packet_Writer(Module):
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def __init__(self, buffer_depth):
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self.word_len = Signal(log2_int(buffer_depth))
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self.stb = Signal()
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self.stb_testseq = Signal()
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self.busy = Signal()
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# # #
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self.specials.mem = mem = Memory(word_width, buffer_depth)
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self.specials.mem_port = mem_port = mem.get_port()
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self.source = Endpoint(word_layout)
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# increment addr in the same cycle the moment addr_inc is high
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# as memory takes one cycle to shift to the correct addr
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addr_next = Signal(log2_int(buffer_depth))
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addr = Signal.like(addr_next)
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addr_rst = Signal()
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addr_inc = Signal()
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self.sync += addr.eq(addr_next),
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self.comb += [
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addr_next.eq(addr),
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If(addr_rst,
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addr_next.eq(addr_next.reset),
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).Elif(addr_inc,
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addr_next.eq(addr + 1),
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),
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mem_port.adr.eq(addr_next),
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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cnt = Signal(max=0xFFF)
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fsm.act("IDLE",
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addr_rst.eq(1),
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If(self.stb, NextState("TRANSMIT")),
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If(self.stb_testseq,
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NextValue(cnt, cnt.reset),
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NextState("WRITE_TEST_PACKET_TYPE"),
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)
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)
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fsm.act("TRANSMIT",
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self.source.stb.eq(1),
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self.source.data.eq(mem_port.dat_r),
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If(self.source.ack,
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addr_inc.eq(1),
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),
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If(addr_next == self.word_len,
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self.source.eop.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("WRITE_TEST_PACKET_TYPE",
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(C(0x04, char_width), 4)),
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self.source.k.eq(Replicate(0, 4)),
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If(self.source.ack,NextState("WRITE_TEST_COUNTER"))
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)
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fsm.act("WRITE_TEST_COUNTER",
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self.source.stb.eq(1),
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self.source.data[:8].eq(cnt[:8]),
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self.source.data[8:16].eq(cnt[:8]+1),
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self.source.data[16:24].eq(cnt[:8]+2),
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self.source.data[24:].eq(cnt[:8]+3),
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self.source.k.eq(Cat(0, 0, 0, 0)),
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If(self.source.ack,
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If(cnt == 0xFFC,
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self.source.eop.eq(1),
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NextState("IDLE")
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).Else(
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NextValue(cnt, cnt + 4),
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)
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)
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)
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class RX_Debug_Buffer(Module,AutoCSR):
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def __init__(self, layout, size):
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self.submodules.buf_out = buf_out = SyncFIFO(layout, size, True)
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self.sink = buf_out.sink
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self.inc = CSR()
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self.dout_valid = CSRStatus()
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self.dout_pak = CSRStatus(word_width)
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self.kout_pak = CSRStatus(word_width//8)
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self.crc_error = CSRStatus()
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self.eop = CSRStatus()
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self.sync += [
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buf_out.source.ack.eq(self.inc.re),
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self.dout_valid.status.eq(buf_out.source.stb),
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# output
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self.eop.status.eq(buf_out.source.eop),
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self.dout_pak.status.eq(buf_out.source.data),
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self.kout_pak.status.eq(buf_out.source.k),
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# self.crc_error.status.eq(buf_out.source.error)
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]
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class Duplicated_Char_Decoder(Module):
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def __init__(self):
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self.sink = Endpoint(word_layout)
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self.source = Endpoint(word_layout_dchar)
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# # #
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# For duplicated characters, an error correction method (e.g. majority voting) is required to meet the CXP spec:
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# RX decoder should immune to single bit errors when handling duplicated characters - Section 9.2.2.1 (CXP-001-2021)
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#
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#
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# 32
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# +---> buffer -----/-----+
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# 32 | | 32+8(dchar)
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# sink ---/---+ ---> source -----/-----> down
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# | 8(dchar) | decoders
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# +---> majority -----/-----+
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# voting
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#
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#
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# Due to the tight setup/hold time requiremnt for 12.5Gbps CXP, the voting logic cannot be implemented as combinational logic
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# Hence, a pipeline approach is needed to avoid any s/h violation, where the majority voting result are pre-calculate and injected into the bus immediate after the PHY.
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# And any downstream modules can access the voting result anytime
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# cycle 1 - buffer data & calculate intermediate result
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buffer = Endpoint(word_layout)
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self.sync += [
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If(buffer.ack,
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self.sink.connect(buffer, omit={"ack"}),
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)
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]
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self.comb += self.sink.ack.eq(buffer.ack)
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# calculate ABC, ABD, ACD, BCD
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char = [[self.sink.data[i*8:(i+1)*8], self.sink.k[i]] for i in range(4)]
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voters = [Record([("data", 8), ("k", 1)]) for _ in range(4)]
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for i, comb in enumerate(combinations(char, 3)):
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self.sync += [
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If(buffer.ack,
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voters[i].data.eq(reduce(and_, [code[0] for code in comb])),
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voters[i].k.eq(reduce(and_, [code[1] for code in comb])),
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)
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]
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# cycle 2 - inject the voting result
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self.sync += [
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If(self.source.ack,
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buffer.connect(self.source, omit={"ack", "dchar", "dchar_k"}),
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self.source.dchar.eq(Replicate(reduce(or_, [v.data for v in voters]), 4)),
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self.source.dchar_k.eq(Replicate(reduce(or_, [v.k for v in voters]), 4)),
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)
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]
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self.comb += buffer.ack.eq(self.source.ack)
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class Packet_Arbiter(Module):
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def __init__(self):
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self.decode_err = Signal()
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self.recv_test_pak = Signal()
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self.recv_heartbeat = Signal()
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self.sink = Endpoint(word_layout_dchar)
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self.source_stream = Endpoint(word_layout_dchar)
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self.source_test = Endpoint(word_layout_dchar)
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self.source_heartbeat = Endpoint(word_layout_dchar)
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self.source_command = Endpoint(word_layout_dchar)
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# # #
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type = {
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"data_stream": 0x01,
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"control_ack_no_tag": 0x03,
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"test_packet": 0x04,
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"control_ack_with_tag": 0x06,
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"event": 0x07,
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"heartbeat": 0x09,
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}
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# Data packet parser
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.sink.ack.eq(1),
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If((self.sink.stb & (self.sink.dchar == KCode["pak_start"]) & (self.sink.dchar_k == 1)),
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NextState("DECODE"),
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)
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)
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fsm.act("DECODE",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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Case(self.sink.dchar, {
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type["data_stream"]: NextState("COPY_STREAM_PACKET"),
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type["test_packet"]: [
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self.recv_test_pak.eq(1),
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NextState("COPY_TEST_PACKET"),
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],
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type["control_ack_no_tag"]:[
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# pass packet type for downstream decoder
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self.source_command.stb.eq(1),
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self.source_command.data.eq(self.sink.data),
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NextState("COPY_COMMAND_PACKET"),
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],
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type["control_ack_with_tag"]:[
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# pass packet type for downstream decoder
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self.source_command.stb.eq(1),
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self.source_command.data.eq(self.sink.data),
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NextState("COPY_COMMAND_PACKET"),
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],
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type["event"]: [
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# pass packet type for downstream decoder
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self.source_command.stb.eq(1),
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self.source_command.data.eq(self.sink.data),
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NextState("COPY_COMMAND_PACKET"),
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],
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type["heartbeat"] : [
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self.recv_heartbeat.eq(1),
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NextState("COPY_HEARTBEAT_PACKET"),
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],
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"default": [
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self.decode_err.eq(1),
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# wait till next valid packet
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NextState("IDLE"),
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],
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}),
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)
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)
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# copy stream data packet with K29.7
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fsm.act("COPY_STREAM_PACKET",
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||||
self.sink.connect(self.source_stream),
|
||||
If((self.sink.stb & self.source_stream.ack & (self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
# copy test sequence packet with K29.7
|
||||
fsm.act("COPY_TEST_PACKET",
|
||||
self.sink.connect(self.source_test),
|
||||
If((self.sink.stb & self.source_test.ack & (self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
# copy command packet with K29.7
|
||||
fsm.act("COPY_COMMAND_PACKET",
|
||||
self.sink.connect(self.source_command),
|
||||
If((self.sink.stb & self.source_command.ack & (self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
# copy heartbeat packet with K29.7
|
||||
fsm.act("COPY_HEARTBEAT_PACKET",
|
||||
self.sink.connect(self.source_heartbeat),
|
||||
If((self.sink.stb & self.source_heartbeat.ack & (self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
@FullMemoryWE()
|
||||
class Command_Packet_Reader(Module):
|
||||
def __init__(self, buffer_depth, nslot):
|
||||
self.write_ptr = Signal(log2_int(nslot))
|
||||
self.read_ptr = Signal.like(self.write_ptr)
|
||||
self.buffer_err = Signal()
|
||||
|
||||
self.sink = Endpoint(word_layout_dchar)
|
||||
|
||||
# # #
|
||||
|
||||
# N buffers for firmware to read packet from
|
||||
|
||||
self.specials.mem = mem = Memory(word_width, nslot*buffer_depth)
|
||||
self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
|
||||
buf_mem_we = Signal.like(mem_port.we)
|
||||
buf_mem_dat_w = Signal.like(mem_port.dat_w)
|
||||
buf_mem_adr = Signal.like(mem_port.adr)
|
||||
|
||||
# buffered mem_port to improve timing
|
||||
self.sync += [
|
||||
mem_port.we.eq(buf_mem_we),
|
||||
mem_port.dat_w.eq(buf_mem_dat_w),
|
||||
mem_port.adr.eq(buf_mem_adr)
|
||||
]
|
||||
|
||||
addr_nbits = log2_int(buffer_depth)
|
||||
addr = Signal(addr_nbits)
|
||||
self.comb += [
|
||||
buf_mem_adr[:addr_nbits].eq(addr),
|
||||
buf_mem_adr[addr_nbits:].eq(self.write_ptr),
|
||||
]
|
||||
|
||||
# Data packet parser
|
||||
self.submodules.fsm = fsm = FSM(reset_state="LOAD_BUFFER")
|
||||
|
||||
fsm.act("LOAD_BUFFER",
|
||||
buf_mem_we.eq(0),
|
||||
self.sink.ack.eq(1),
|
||||
If(self.sink.stb,
|
||||
If(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
|
||||
NextState("MOVE_BUFFER_PTR"),
|
||||
).Else(
|
||||
buf_mem_we.eq(1),
|
||||
buf_mem_dat_w.eq(self.sink.data),
|
||||
NextValue(addr, addr + 1),
|
||||
If(addr == buffer_depth - 1,
|
||||
# discard the packet
|
||||
self.buffer_err.eq(1),
|
||||
NextValue(addr, addr.reset),
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("MOVE_BUFFER_PTR",
|
||||
self.sink.ack.eq(0),
|
||||
If(self.write_ptr + 1 == self.read_ptr,
|
||||
# if next one hasn't been read, overwrite the current buffer when new packet comes in
|
||||
self.buffer_err.eq(1),
|
||||
).Else(
|
||||
NextValue(self.write_ptr, self.write_ptr + 1),
|
||||
),
|
||||
NextValue(addr, addr.reset),
|
||||
NextState("LOAD_BUFFER"),
|
||||
)
|
||||
|
||||
|
||||
class Heartbeat_Packet_Reader(Module):
|
||||
def __init__(self):
|
||||
self.sink = Endpoint(word_layout_dchar)
|
||||
|
||||
self.host_id = Signal(4*char_width)
|
||||
self.heartbeat = Signal(8*char_width)
|
||||
|
||||
# # #
|
||||
|
||||
n_chars = 12
|
||||
packet_layout = [
|
||||
("stream_id", len(self.host_id)),
|
||||
("source_tag", len(self.heartbeat)),
|
||||
]
|
||||
assert layout_len(packet_layout) == n_chars*char_width
|
||||
|
||||
|
||||
cnt = Signal(max=n_chars)
|
||||
packet_buffer = Signal(layout_len(packet_layout))
|
||||
case = dict(
|
||||
(i, packet_buffer[8*i:8*(i+1)].eq(self.sink.dchar))
|
||||
for i in range(n_chars)
|
||||
)
|
||||
self.sync += [
|
||||
self.host_id.eq(switch_endianness(packet_buffer[:4*char_width])),
|
||||
self.heartbeat.eq(switch_endianness(packet_buffer[4*char_width:])),
|
||||
|
||||
self.sink.ack.eq(1),
|
||||
If(self.sink.stb,
|
||||
Case(cnt, case),
|
||||
If(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
|
||||
cnt.eq(cnt.reset),
|
||||
).Else(
|
||||
cnt.eq(cnt + 1),
|
||||
),
|
||||
),
|
||||
]
|
||||
|
||||
|
||||
class Test_Sequence_Checker(Module):
|
||||
def __init__(self):
|
||||
self.error = Signal()
|
||||
|
||||
self.sink = Endpoint(word_layout_dchar)
|
||||
|
||||
# # #
|
||||
|
||||
# Section 9.9.1 (CXP-001-2021)
|
||||
# the received test data packet (0x00, 0x01 ... 0xFF)
|
||||
# need to be compared against the local test sequence generator
|
||||
cnt_bytes = [Signal(char_width, reset=i) for i in range(4)]
|
||||
test_errors = [Signal() for _ in range(4)]
|
||||
|
||||
self.sync += [
|
||||
self.sink.ack.eq(1),
|
||||
self.error.eq(reduce(or_, test_errors))
|
||||
]
|
||||
for i, (cnt, err) in enumerate(zip(cnt_bytes,test_errors)):
|
||||
self.sync += [
|
||||
err.eq(0),
|
||||
If(self.sink.stb,
|
||||
If(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
|
||||
cnt.eq(cnt.reset)
|
||||
).Else(
|
||||
If(self.sink.data[8 * i : 8 * (i + 1)] != cnt,
|
||||
err.eq(1),
|
||||
),
|
||||
If(cnt == 0xFC + i,
|
||||
cnt.eq(cnt.reset),
|
||||
).Else(
|
||||
cnt.eq(cnt + 4)
|
||||
),
|
||||
)
|
||||
)
|
||||
]
|
||||
|
||||
class Trigger_Reader(Module):
|
||||
def __init__(self):
|
||||
self.sink = Endpoint(word_layout_dchar)
|
||||
self.source = Endpoint(word_layout_dchar)
|
||||
|
||||
self.trig = Signal()
|
||||
self.delay = Signal(char_width)
|
||||
self.linktrigger_n = Signal(char_width)
|
||||
|
||||
# # #
|
||||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="COPY")
|
||||
|
||||
fsm.act("COPY",
|
||||
If((self.sink.stb & (self.sink.dchar == KCode["trig_indic_28_2"]) & (self.sink.dchar_k == 1)),
|
||||
# discard K28,2
|
||||
self.sink.ack.eq(1),
|
||||
NextState("READ_DELAY")
|
||||
).Else(
|
||||
self.sink.connect(self.source),
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("READ_DELAY",
|
||||
self.sink.ack.eq(1),
|
||||
If(self.sink.stb,
|
||||
NextValue(self.delay, self.sink.dchar),
|
||||
NextState("READ_LINKTRIGGER"),
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("READ_LINKTRIGGER",
|
||||
self.sink.ack.eq(1),
|
||||
If(self.sink.stb,
|
||||
NextValue(self.linktrigger_n, self.sink.dchar),
|
||||
self.trig.eq(1),
|
||||
NextState("COPY"),
|
||||
)
|
||||
)
|
||||
|
||||
class Trigger_ACK_Reader(Module):
|
||||
def __init__(self):
|
||||
self.sink = Endpoint(word_layout_dchar)
|
||||
self.source = Endpoint(word_layout_dchar)
|
||||
|
||||
self.ack = Signal()
|
||||
|
||||
# # #
|
||||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="COPY")
|
||||
|
||||
fsm.act("COPY",
|
||||
If((self.sink.stb & (self.sink.dchar == KCode["io_ack"]) & (self.sink.dchar_k == 1)),
|
||||
# discard K28,6
|
||||
self.sink.ack.eq(1),
|
||||
NextState("READ_ACK")
|
||||
).Else(
|
||||
self.sink.connect(self.source),
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("READ_ACK",
|
||||
self.sink.ack.eq(1),
|
||||
If(self.sink.stb,
|
||||
NextState("COPY"),
|
||||
# discard the word after K28,6
|
||||
If((self.sink.dchar == 0x01) & (self.sink.dchar_k == 0),
|
||||
self.ack.eq(1),
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
class Buffer(Module):
|
||||
def __init__(self, layout):
|
||||
self.sink = Endpoint(layout)
|
||||
self.source = Endpoint(layout)
|
||||
|
||||
# # #
|
||||
|
||||
self.sync += [
|
||||
If(self.source.ack,
|
||||
self.sink.connect(self.source, omit={"ack"}),
|
||||
),
|
||||
]
|
||||
self.comb += [
|
||||
self.sink.ack.eq(self.source.ack),
|
||||
]
|
||||
|
||||
class EOP_Marker(Module):
|
||||
def __init__(self):
|
||||
self.sink = Endpoint(word_layout_dchar)
|
||||
self.source = Endpoint(word_layout_dchar)
|
||||
|
||||
# # #
|
||||
|
||||
self.sync += [
|
||||
If(self.source.ack,
|
||||
If(~((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
|
||||
self.sink.connect(self.source, omit={"ack", "eop"}),
|
||||
).Else(
|
||||
# don't pass K29.7 to downstream
|
||||
self.source.stb.eq(0),
|
||||
)
|
||||
),
|
||||
]
|
||||
self.comb += [
|
||||
self.sink.ack.eq(self.source.ack),
|
||||
self.source.eop.eq(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1))),
|
||||
]
|
||||
Loading…
Reference in New Issue
Block a user