cxp GW: link upconn reset tgt

cxp GW: refactor gtx drp

cxp GW: remove reset

cxp GW: restart read ptr until gtx is ready

cxp GW: add rtlink

cxp GW: fix linktrig to use 1 bit only

cxp GW: separate CXP into Master & extension

src/gateware/cxp.py

@@ -2,6 +2,8 @@ from migen import *
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from misoc.interconnect.csr import *
 
+from artiq.gateware.rtio import rtlink
+
 from cxp_downconn import CXP_DownConn_PHYS
 from cxp_upconn import CXP_UpConn_PHYS
 from cxp_pipeline import *
@@ -10,16 +12,14 @@ from cxp_pipeline import *
 class CXP_PHYS(Module, AutoCSR):
     def __init__(self, refclk, upconn_pads, downconn_pads, sys_clk_freq, debug_sma, pmod_pads):
         assert len(upconn_pads) == len(downconn_pads)
+
         self.submodules.upconn = CXP_UpConn_PHYS(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
         self.submodules.downconn = CXP_DownConn_PHYS(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
 
 @FullMemoryWE()
 class CXP_Interface(Module, AutoCSR):
     def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
-        # TODO: add rtio interface io 
-        
         self.submodules.upconn = UpConn_Interface(upconn_phy, debug_sma, pmod_pads)
-
         self.submodules.downconn = DownConn_Interface(downconn_phy, debug_sma, pmod_pads)
 
     def get_tx_port(self):
@@ -43,6 +43,34 @@ class CXP_Interface(Module, AutoCSR):
     def get_loopback_tx_mem_size(self):
         return self.downconn.bootstrap_loopback.mem.depth*self.downconn.bootstrap_loopback.mem.width // 8
 
+class CXP_Master(CXP_Interface):
+    def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
+        CXP_Interface.__init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads)
+        nbit_trigdelay = 8
+        nbit_linktrig = 1
+
+        self.rtlink = rtlink.Interface(
+            rtlink.OInterface(nbit_trigdelay + nbit_linktrig),
+            rtlink.IInterface(word_dw, timestamped=False)
+        )
+
+        self.sync.rio += [
+            If(self.rtlink.o.stb,
+                self.upconn.trig.delay.eq(self.rtlink.o.data[nbit_linktrig:]),
+                self.upconn.trig.linktrig_mode.eq(self.rtlink.o.data[:nbit_linktrig]),
+            ),
+            self.upconn.trig.stb.eq(self.rtlink.o.stb),
+        ]
+
+        # DEBUG: out
+        self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.p_tx),
+        # self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.n_rx),
+
+class CXP_Extension(CXP_Interface):
+    def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
+        CXP_Interface.__init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads)
+
+
 class DownConn_Interface(Module, AutoCSR):
     def __init__(self, phy, debug_sma, pmod_pads):
         self.rx_start_init = CSRStorage()
@@ -95,22 +123,14 @@ class DownConn_Interface(Module, AutoCSR):
 
         self.comb += gtx.dclk.eq(ClockSignal("sys"))
         self.sync += [
-            gtx.den.eq(0),
-            gtx.dwen.eq(0),
-            If(self.gtx_dread.re,
-                gtx.den.eq(1),
-                gtx.daddr.eq(self.gtx_daddr.storage),
-            ).Elif(self.gtx_din_stb.re,
-                gtx.den.eq(1),
-                gtx.dwen.eq(1),
             gtx.daddr.eq(self.gtx_daddr.storage),
+            gtx.den.eq(self.gtx_dread.re | self.gtx_din_stb.re),
+            gtx.dwen.eq(self.gtx_din_stb.re),
             gtx.din.eq(self.gtx_din.storage),
-            ),
             If(gtx.dready,
                 self.gtx_dready.w.eq(1),
                 self.gtx_dout.status.eq(gtx.dout),
-            ),
+            ).Elif(self.gtx_dready.re,
-            If(self.gtx_dready.re,
                 self.gtx_dready.w.eq(0),
             ),
         ]
@@ -254,7 +274,7 @@ class DownConn_Interface(Module, AutoCSR):
         ]
         self.sync += [
             self.pending_packet.w.eq(self.read_ptr.status != bootstrap.write_ptr_sys),
-            If(self.rx_restart.re,
+            If(~gtx.rx_ready,
                 self.read_ptr.status.eq(0),
             ).Elif(self.pending_packet.re & self.pending_packet.w, 
                 self.read_ptr.status.eq(self.read_ptr.status + 1),
@@ -296,7 +316,7 @@ class DownConn_Interface(Module, AutoCSR):
         ]
 
         self.specials += [
-            Instance("OBUF", i_I=phy.gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
+            # Instance("OBUF", i_I=phy.gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
             # Instance("OBUF", i_I=, o_O=debug_sma.p_rx),
             # # pmod 0-7 pin
             Instance("OBUF", i_I=bootstrap.test_err, o_O=pmod_pads[0]),
@@ -312,20 +332,6 @@ class DownConn_Interface(Module, AutoCSR):
         
 class UpConn_Interface(Module, AutoCSR):
     def __init__(self, phy, debug_sma, pmod_pads):
-        self.clk_reset = CSRStorage(reset=1)
-        self.bitrate2x_enable = CSRStorage()
-        self.tx_enable = CSRStorage()
-        self.tx_mux = CSRStorage()
-
-        # # #
-
-        self.sync += [
-            phy.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
-            phy.tx_enable.eq(self.tx_enable.storage),
-            phy.clk_reset.eq(self.clk_reset.re),
-        ]
-
-
         # Transmission Pipeline
         #
         #              32                                                  32           8
@@ -350,13 +356,13 @@ class UpConn_Interface(Module, AutoCSR):
         # # DEBUG: INPUT
         self.trig_stb = CSR()
         self.trig_delay = CSRStorage(8) 
-        self.linktrigger = CSRStorage(2)
+        self.linktrigger = CSRStorage()
 
-        self.sync += [
+        # self.sync += [
-            trig.stb.eq(self.trig_stb.re),
+        #     trig.stb.eq(self.trig_stb.re),
-            trig.delay.eq(self.trig_delay.storage),
+        #     trig.delay.eq(self.trig_delay.storage),
-            trig.linktrig_mode.eq(self.linktrigger.storage),
+        #     trig.linktrig_mode.eq(self.linktrigger.storage),
-        ]
+        # ]
 
         
         # 1: IO acknowledgment for trigger packet