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artiq-zynq
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downconn fw: add debug tx packet

This commit is contained in:
morgan 2024-09-16 12:39:42 +08:00
parent ca32914917
commit 9a06848cbb
1 changed files with 29 additions and 64 deletions
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93
src/libboard_artiq/src/cxp_downconn.rs
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@ -3,7 +3,7 @@ use libboard_zynq::{println, timer::GlobalTimer};
use log::info;
// use log::info;
use crate::pl::csr;
use crate::{cxp_proto, pl::csr};
#[derive(Clone, Copy, Debug)]
#[allow(non_camel_case_types)]
@ -37,71 +37,36 @@ pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
while csr::cxp::downconn_phy_rx_ready_read() != 1 {}
info!("rx ready!");
loop {
// for _ in 0..20 {
// NOTE: raw bits
// let data0 = csr::cxp::downconn_phy_rxdata_0_read();
// let data1 = csr::cxp::downconn_phy_rxdata_1_read();
// let data2 = csr::cxp::downconn_phy_rxdata_2_read();
// let data3 = csr::cxp::downconn_phy_rxdata_3_read();
// let rxready = csr::cxp::downconn_phy_rx_ready_read();
// timer.delay_us(100);
// if data0 == 0b0101111100 || data0 == 0b1010000011 {
// println!(
// "data[0] = {:#012b} comma = {} | rx ready = {}",
// data0,
// data0 == 0b0101111100 || data0 == 0b1010000011,
// rxready,
// );
// timer.delay_us(1_000_000);
// } else if data0 == 0b1001111100 || data0 == 0b0110000011 {
// println!(
// "data[0] = {:#012b} K28.1 | rx ready = {}",
// data0,
// rxready,
// );
// timer.delay_us(1_000_000);
// } else {
// println!(
// "data[0] = {:#012b} | rx ready = {}",
// data0,
// rxready,
// );
// timer.delay_us(1_000_000);
// }
cxp_proto::downconn_debug_send(&cxp_proto::Packet::CtrlRead {
addr: 0x00,
length: 0x04,
});
timer.delay_us(1_000_000);
// NOTE: raw bits
// let data0 = csr::cxp::downconn_phy_rxdata_0_read();
// let data1 = csr::cxp::downconn_phy_rxdata_1_read();
// let data2 = csr::cxp::downconn_phy_rxdata_2_read();
// let data3 = csr::cxp::downconn_phy_rxdata_3_read();
// println!(
// "0b{:010b} {:010b} {:010b} {:010b}",
// data0, data1, data2, data3
// );
// NOTE:decode data
// let data0_k = csr::cxp::downconn_phy_decoded_k_0_read();
// let data1_k = csr::cxp::downconn_phy_decoded_k_1_read();
// let data2_k = csr::cxp::downconn_phy_decoded_k_2_read();
// let data3_k = csr::cxp::downconn_phy_decoded_k_3_read();
let data0_decoded = csr::cxp::downconn_phy_decoded_data_0_read();
let data1_decoded = csr::cxp::downconn_phy_decoded_data_1_read();
let data2_decoded = csr::cxp::downconn_phy_decoded_data_2_read();
let data3_decoded = csr::cxp::downconn_phy_decoded_data_3_read();
println!(
"{:#04x} {:#04x} {:#04x} {:#04x}",
data0_decoded, data1_decoded, data2_decoded, data3_decoded,
);
// println!(
// "decoded_data[0] = {:#04x} decoded_k[0] = {:#b} decoded_data[1] = {:#04x} decoded_k[1] = {:#b}",
// data0_decoded,
// data0_k,
// data1_decoded,
// data1_k,
// );
timer.delay_us(200); // wait packet has arrive at async fifo in
unsafe {
csr::cxp::downconn_phy_tx_stb_write(1);
timer.delay_us(200);
csr::cxp::downconn_phy_tx_stb_write(0);
}
// TODO: investigate how to make my packet appear
// TODO: discard idle word
const LEN: usize = 20;
let mut pak_arr: [u32; LEN] = [0; LEN];
let mut i: usize = 0;
unsafe {
while csr::cxp::downconn_debug_out_dout_valid_read() == 1 {
pak_arr[i] = csr::cxp::downconn_debug_out_dout_pak_read();
// println!("received {:#04X}", pak_arr[i]);
csr::cxp::downconn_debug_out_inc_write(1);
i += 1;
if i == LEN {
break;
}
}
}
cxp_proto::print_packetu32(&pak_arr)
}
}